參數(shù)資料
型號(hào)： HSP50214VC
廠商： INTERSIL CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Programmable Downconverter
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP120
封裝： MQFP-120
文件頁(yè)數(shù)： 41/54頁(yè)
文件大?。?/td> 395K
代理商： HSP50214VC
41
CONTROL WORD 1: INPUT LEVEL DETECTOR (SYNCHRONOUS TO CLKIN)
BIT
POSITION
FUNCTION
DESCRIPTION
31
Reserved
Reserved.
30
Integration Mode
0- Integration of magnitude error stops when the interval counter times out.
1- Integration runs continuously. When the interval counter times out, the integrator reloads, and
the results of the integration is sent to a register for the processor to read.
29-14
Integration Interval
These are the top 16 bits of the 18-bit integration counter, ICPrel. ICPrel = (N)/4+1; where N is
the desired integration period in CLKIN cycles, defined as the number of input samples to be
integrated. N must be a multiple of 4: [0, 4, 8, 12, 16 .... , 2
18
]. Bit 29 is the MSB. If the input is
interpolated, then the zeros must be accounted for, as they will be added to the threshold! If the
gated input mode is used, the same input sample will be accumulated multiple times.
13-0
Input Threshold
Input magnitude threshold. Bits 12-0 correspond to input bits 12-0. The magnitude of the input
is added to this threshold, where the threshold is a signed number. Bit 13 is the MSB.
CONTROL WORD 2: INPUT LEVEL DETECTOR START STROBE (SYNCHRONIZED TO CLKIN)
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
Start Input Level
Detector AGC
Integrator
Writing to this location starts/restarts the input AGC error integrator. The integrator will either
restart or stop when the integration interval counter times out depending on bit 30 of control reg-
ister 1 (see Microprocessor Write Section).
CONTROL WORD 3: CARRIER NCO CENTER FREQUENCY (SYNCHRONIZED TO CLKIN)
BIT
POSITION
FUNCTION
DESCRIPTION
31-0
Carrier Center
Frequency
These bits control the frequency of the Carrier NCO. The frequency range of the NCO is
±
F
S
/2
where F
S
is the input sample rate. The bits are computed by the equation N = (F
NCO
/ F
S
)*2
32
.
Bit 31 is the MSB. This location is a holding register. After loading, a transfer to the active reg-
ister is done by writing to Control Word 5 or by generating a SYNCIN1 with Control Word 0 bit
20 set to 1.
CONTROL WORD 4: CARRIER PHASE OFFSET (SYNCHRONIZED TO CLKIN)
BIT
POSITION
FUNCTION
DESCRIPTION
31-10
Reserved
Reserved
9-0
Carrier Phase Offset
These bits, PO, are used to offset the phase of the carrier NCO. The bits are computed by the
equation PO= INT[(2
10
φ
off
)/ 2
π
]
HEX
; (-
π
<
φ
off
<
π
) for 10-bit 2’s complement representation or
from 0 to 2
π
for 10-bit offset binary representation. Bit 9 is the MSB. This location is a holding
register. After loading, a transfer to the active register is done by writing to Control Word 6 or by
generating a SYNCIN1 with Control Word 0 bit 20 set to 1.
CONTROL WORD 5: CARRIER FREQUENCY STROBE (SYNCHRONIZED TO CLKIN)
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
Carrier Frequency
Strobe
Writing to this address updates the carrier frequency control word from the holding register.
CONTROL WORD 6: CARRIER PHASE STROBE (SYNCHRONIZED TO CLKIN)
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
Carrier Phase
Strobe
Writing to this address updates the carrier phase offset control word with the value written to
the phase offset (PO) register.
HSP50214
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