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參數(shù)資料
| 型號(hào)： | HSP50214VC |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Programmable Downconverter |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP120 |
| 封裝： | MQFP-120 |
| 文件頁數(shù)： | 21/54頁 |
| 文件大?。?/td> | 395K |
| 代理商： | HSP50214VC |
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21
For example, if M
LG
= 0101 and E
LG
= 1100, the AGC
Loop Gain = 0.3125*2
-7
. The loop gain mantissas and
exponents are set in the AGC Loop Parameter control reg-
ister (Control Word 8, bits 0-15). Two AGC loop gains are
provided in the Programmable Down Converter, for quick
adjustment of the AGC loop. The AGC Gain select is a con-
trol input to the device, selecting Gain 0 when AGCGNSEL
= 0, and selecting Gain 1 when AGCGNSEL = 1.
Resampler/Halfband Filter
The Resampler is an NCO controlled polyphase filter that
allows the output sample rate to have a non-integer relation-
ship to the input sample rate. The filter engine can be viewed
conceptually as a fixed interpolation filter, followed by an
NCO controlled decimator.
The prototype polyphase filter has 192 taps designed at 32
times the input sample rate. Each of the 32 phases has 6 fil-
ter taps (6)(32) = 192. The stopband attenuation of the pro-
totype filter is greater than 60dB, as shown in Figure 24. The
signal to total image power ratio is approximately 55dB, due
to the aliasing of the interpolation images. The filter is capa-
ble of decimation rates from 1 to 4. If the output is at least 2x
the baud rate, the 32 interpolation phases yield an effective
sample rate of 64x the baud rate or approximately 1.5%,
(1/64), maximum timing error.
Following the Resampler are two interpolation halfband fil-
ters. The halfband filters allow the user to up-sample by 2 or
4 to recover time resolution lost by decimating. Interpolating
by 2 or 4 gives 1/4 or 1/8 baud time resolution (assuming 2x
baud at the Resampler output). The halfband filters use the
same coefficients as HB3 and HB5 from the Halfband Filters
Section. If one halfband is used, the 23-tap filter is chosen. If
two are used, the 23-tap filter runs first followed by the
15-tap filter operating at twice the first halfband’s rate. The
23-tap filter requires 7 multiplies, and the 15-tap filter
requires 5 multiplies to complete a filter calculation.
Using the interpolation halfband filters allows for reduction in
the FIR filter sample rate. This optimizes the use of the pro-
grammable FIR filter by allowing the FIR output sample rate
to be closer to the Nyquist rate of the desired bandwidth.
Optimizing the FIR filter performance provides better use of
the programmable FIR taps. Table 10 details the maximum
clocking rates for the possible re-sampling and interpolation
halfband filter configurations of this section of the PDC. Con-
trol Word 16, bits 2-0 identify the filter configuration. Control
Word 16, bit 3 is used to bypass the polyphase Resampler
filter.
For proper data output from the interpolation filters, the data
ready signal must account for the re-sampling and interpola-
tion processes. Figure 25 illustrates the insertion of addi-
tional data ready pulses to provide sufficient pulses for the
new output sample rate. The Resampler Output Pulse Delay
parameter is set in Control Word 16, bits 4-11. These bits set
the delay between the output samples when interpolation is
utilized. Program this distance between pulses using
A value of at least 5 is required to have sufficient time to
update the output buffer register. (Writing 5 samples
requires 5 clock cycles) A value of at least 16 is required for
proper serial output from the part. (Conversion from 16-bit
parallel to serial) The value is programmed in numbers of
PROCCLK’s.
TABLE 7. AGC LOOP GAIN BINARY MANTISSA TO GAIN
SCALE FACTOR MAPPING
BINARY
CODE
(MMMM)
SCALE
FACTOR
BINARY
CODE
(MMMM)
SCALE
FACTOR
0000
0.0000
1000
0.5000
0001
0.0625
1001
0.5625
0010
0.1250
1010
0.6250
0011
0.1875
1011
0.6875
0100
0.2500
1100
0.7500
0101
0.3125
1101
0.8125
0110
0.3750
1110
0.8750
0111
0.4375
1111
0.9375
TABLE 8. AGC LOOP GAIN BINARY EXPONENT TO GAIN
SCALE FACTOR MAPPING
BINARY
CODE
(EEEE)
SCALE
FACTOR
BINARY
CODE
(EEEE)
SCALE
FACTOR
0000
2
15
1000
2
7
0001
2
14
1001
2
6
0010
2
13
1010
2
5
0011
2
12
1011
2
4
0100
2
11
1100
2
3
0101
2
10-
1101
2
2
0110
2
9
1110
2
1
0111
2
8
1111
2
0
(EQ. 20)
N
f
PROCCLK
/f
OUT
(
)
1
]
–
[
=
HSP50214
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50214VI | Programmable Downconverter |
| HSP50214 | Programmable Downconverter |
| HSP50215VC | Digital UpConverter |
| HSP50215VI | Digital UpConverter |
| HSP50215EVAL | DSP Modulator Evaluation Board |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215EVAL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215VC | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter |
| HSP50215VI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter |
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