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參數(shù)資料
| 型號： | HSP50214VC |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Programmable Downconverter |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP120 |
| 封裝： | MQFP-120 |
| 文件頁數(shù)： | 17/54頁 |
| 文件大?。?/td> | 395K |
| 代理商： | HSP50214VC |
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17
255-Tap Programmable FIR Filter
The Programmable FIR filter can be used to implement real
filters with even or odd symmetry, using up to 255 filter taps,
or complex filters with up to 64 taps. The FIR filter takes
advantage of symmetry in coefficients by summing data
samples that share a common coefficient, prior to multiplica-
tion. In this manner, two filter taps are calculated per multiply
accumulate cycle. Asymmetric filters cannot share common
coefficients, so only one tap per multiply accumulate cycle is
calculated. The filter can be effectively bypassed by setting
the coefficient C
0
= 1 and all other coefficients, C
N
= 0.
Additionally, the Programmable FIR filter provides for deci-
mation rates, R, from 1 to 16. The processing rate of the Fil-
ter Compute Engine is PROCCLK. As a result, the frequency
of PROCCLK must exceed a minimum value to insure that a
filter calculation is complete before the result is required for
output. In configurations which do not use decimation, one
input sample period is available for filter calculation before
an output is required. For configurations which employ deci-
mation, up to 16 input sample periods may be available for
filter calculation.
For real filter configurations, use Equation 11 to calculate the
number of taps available at a given input filter sample rate.
for real filters, and
for complex filters, where floor is defined as the integer por-
tion of a number; PROCCLK is the compute clock; FSAMP =
the FIR input sample rate; R = Decimation Rate; SYM = 1 for
symmetrical filter, 0 for asymmetrical filter; ODD# = 1 for an
odd number of filter taps, 0 = an even number of taps.
Use Equation 12 to calculate the maximum input rate.
for real filters, and
for complex filters, where floor[x], PROCCLK, FSAMP, R =
Decimation Rate, SYM, and ODD# are defined as in Equa-
tion 11.
Use Equation 13 to calculate the maximum output sample
rate for both real and complex filters.
The coefficients are 22 bits and are loaded using writes to
Control Words 128 through 255 (see Microprocessor Write
Section). For real filters, the same coefficients are used by I
and Q paths. If the filter is configured as a symmetric filter
using Control Word 17 bit 9, then coefficients are loaded
starting with the center coefficient in Control Word 128 and
proceed to last coefficient in Control Word 128+n. The filter
symmetry type can be set to even or odd symmetric, and the
number of filter coefficients can be even or odd, as illustrated
in Figure 20. Note that complex filters can also be realized
but are only allowed to be asymmetric. Only the coefficients
that are used need to be loaded.
TAPS
floor PROCCLK
SYM
)
(
[
–
F
SAMP
R
)
]
(
)
R
]
–
(
)
1
+
(
=
(EQ. 11A)
SYM
)
ODD#
(
TAPS
floor (PROCCLK
F
SAMP
R
(
)
R
]
2
(
)
]
–
=
(EQ. 11B)
(EQ. 12A)
F
SAMP
PROCCLK
(
)
R
( )
R
floor Taps
)
[
+
[
+
=
SYM
(
)
ODD#
(
)]
1
SYM
+
(
)
]]
(EQ. 12B)
F
SAMP
PROCCLK
(
)
R
( )
[
]
R
floor Taps
)
2
( )]
+
[
]
=
(EQ. 13)
F
FIROUT
F
SAMP
(
)
R
=
EVEN SYMMETRIC
EVEN TAP FILTER
ODD SYMMETRIC
EVEN TAP FILTER
EVEN SYMMETRIC
ODD TAP FILTER
ODD SYMMETRIC
ODD TAP FILTER
C0
CN-1
C
C
C0
CN-1
C0
CN-1
COEFFICIENT
NUMBER
COEFFICIENT
NUMBER
COEFFICIENT
NUMBER
COEFFICIENT
NUMBER
C
C
ASYMMETRIC
ODD TAP FILTER
C0
CN-1
COEFFICIENT
NUMBER
C
ASYMMETRIC
EVEN TAP FILTER
C0
CN-1
COEFFICIENT
NUMBER
C
COMPLEX FILTERS
C
Q(0)
C
I(N-1)
COEFFICIENT
NUMBER
I
REAL COEFFICIENT VALUE
C
C
Q(N-1)
REAL FILTERS
Definitions:
Even Symmetric: h(n) = h(N-n-1) for n = 0 to N-1
Odd Symmetric: h(n) = -h(N-n-1) for n = 0 to N-1
Asymmetric:
a filter with no coefficient symmetry
Even Tap filter:
a filter where N is an even number
Odd Tap filter:
a filter where N is an odd number
Real Filter:
a filter implemented with real coefficients
Complex Filters: a filter with quadrature coefficients
FIGURE 20. DEMONSTRATION OF DIFFERENT TYPES OF
DIGITAL FIR FILTERS CONFIGURED IN THE
PROGRAMMABLE DOWNCONVERTER
C
V
C
Q
C
I
C0
CN-1
HSP50214
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50214VI | Programmable Downconverter |
| HSP50214 | Programmable Downconverter |
| HSP50215VC | Digital UpConverter |
| HSP50215VI | Digital UpConverter |
| HSP50215EVAL | DSP Modulator Evaluation Board |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215EVAL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215VC | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter |
| HSP50215VI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter |
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