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參數(shù)資料
| 型號： | HSP50214VC |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Programmable Downconverter |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP120 |
| 封裝： | MQFP-120 |
| 文件頁數(shù)： | 27/54頁 |
| 文件大小： | 395K |
| 代理商： | HSP50214VC |
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27
Parallel Direct Output Port Mode
The Parallel Direct Output Port Mode outputs two 16-bit
words, AOUT and BOUT, of “real time” data. Figure 30
details the parallel output circuitry. Selection of the data
source for the AOUT and BOUT parallel outputs is done via
Control Word 20, bits 22-23, and 20-21, respectively. The
AOUT port can output I, Magnitude, or Frequency data. The
BOUT port can output Q, Phase or Magnitude data. The
upper bytes of AOUT and BOUT are always in the parallel
direct mode. The 16-bit parallel direct mode is selected by
setting Control Word 20, bit 25, to zero. The DATARDY out-
put is asserted during the first clock cycle of new data on the
AOUT bus.
NOTE: I and Q are sample aligned in time. |r| and
φ
are sample aligned in time, but one sample delayed from I or Q. The frequency
sample is delayed in time from I or Q by 1 sample time + 63 tap FIR impulse response. If the FIR is set to decimate and fre-
quencies selected for AOUT, the DATARDY signal will be at the documented rate.
M
M
I
MAG
FREQ
Q
PHAS
MAG
AOUT(15:8)
A(7:0)
M
RAM(15:8)
AOUT(7:0)
B(7:0)
M
BOUT(7:0)
RAM (7:0)
16
16
16
16
16
16
BOUT DIRECT PAR
OUTPUT MODE
DATA SOURCE
AOUT DIRECT PAR
OUTPUT MODE
DATA SOURCE
DATA SOURCE FOR LSB
BOUT(15:8)
B(15:8)
A(15:8)
RAM (15:0)
Controlled via microprocessor interface.
FIGURE 30A. PARALLEL OUTPUT BLOCK DIAGRAM
DATARDY
PROCCLK
I
Q
DATARDY
R
Q
DATARDY
(NOTE 1)
DATARDY
(NOTE 2)
FREQ
Q
DATARDY
(NOTE 3)
I CHOSEN FOR AOUT
R CHOSEN FOR AOUT
FREQ CHOSEN FOR AOUT
17 PROCCLK PERIODS
T (NOTE 4)
NOTES:
1. Computation preempted by new data.
2. Computation completes.
3. If decimation is selected, the DATARDY signal will occur at 1/Deci times the I/Q output sample rate.
4. T is equal to the number of PROCCLK cycles needed to compute the discriminator FIR plus the delay from I/Q to R/
φ
plus 6. The delay
will change depending on whether the
Θ
computation is preempted or not.
FIGURE 30B. TIMING FOR PARALLEL OUTPUT
HSP50214
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PDF描述 |
|---|---|
| HSP50214VI | Programmable Downconverter |
| HSP50214 | Programmable Downconverter |
| HSP50215VC | Digital UpConverter |
| HSP50215VI | Digital UpConverter |
| HSP50215EVAL | DSP Modulator Evaluation Board |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215EVAL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215VC | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter |
| HSP50215VI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter |
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