參數(shù)資料
型號(hào)： HSP50214VC
廠商： INTERSIL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Programmable Downconverter
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP120
封裝： MQFP-120
文件頁數(shù)： 11/54頁
文件大?。?/td> 395K
代理商： HSP50214VC
11
The integration period counter can be set up to run
continuously or to count down and stop. Continuous
integration counter operation lets the counter run, with
sampling occurring every time the counter reaches zero.
Because the processor samples the detector read port
asynchronous to the CLKIN, data can be missed unless the
status bit is monitored by the processor to ensure that a
sample is taken for every integration count down sequence.
In the count down and stop mode, the microprocessor read
commands can be synchronized to system events, such as
the start of a burst for a TDMA application. The integration
counter can be started at any time by writing to Control Word
2. At the end of the integration period (counter = 0000), the
upper 23 bits of the accumulator are transferred to a holding
register for reading by the microprocessor. Note that it is not
the restarting of the counter (by writing to Control Word 2)
that latches the current value, but the end of the integration
count. When the accumulator results are latched, a bit is set
in the status register to notify the processor. Reading the
most significant byte of the 23 bits clears the status bit. See
the Microprocessor Read Section. Figure 11 illustrates a
typical AGC detection process.
Typically, the average input error is read from the Input Level
Detector port for use in AGC applications. By setting the
threshold to 0, however, the average value of the input signal
can be read directly. The calculation is:
where “l(fā)evel” is the 24-bit value read from the 3 level detec-
tor registers and “N” is the number of samples to be inte-
grated. Note that to get the average value of a sinusoid,
multiply the RMS value by 1.111. For a full scale input sinu-
soid, this yields an RMS value of approximately 3dBFS.
NOTE: 1.111 scales the sinusoid average (2/
π
) to 1/
√
2
.
Carrier Synthesizer/Mixer
The carrier synthesizer/mixer section of the HSP50214 is
shown in Figure 12. The NCO has a 32-bit phase accumula-
tor, a 10-bit phase offset adder, and a sine/cosine ROM.
The frequency of the NCO is the sum of a center frequency
control word, loaded via the microprocessor interface (Con-
trol Word 3, bits 0 to 31), and an offset frequency, loaded
serially via the COF and COFSYNC pins. The offset fre-
quency can be zeroed in Control Word 0, bit 1. Both fre-
quency control terms are 32 bits and the addition is modulo
2
32
. The output frequency of the NCO is computed as:
or in terms of the programmed value:
where N is the 32-bit sum of the center and offset frequency
terms, f
IN
is the input sampling frequency, and INT is the
integer of the computation. See the Microprocessor Write
Section on instructions for writing Control Word 3.
A
O
I
M
T
μ
P
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
-2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
fS
-6dB
-12dB
-18dB
-24dB
-30dB
-36dB
-42dB
-48dB
-54dB
-60dB
-66dB
-72dB
-78dB
-84dB
-90dB
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
17
2
16
2
15
2
18
2
0
2
-1
2
-2
2
-3
2
-4
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
17
2
16
2
15
2
18
0
0
0
0
R
P
A
FIGURE 10. INPUT THRESHOLD DETECTOR BIT WEIGHTING
dBFS
RMS
20
(
)
1.111
(
)
level
(
)
N
( )
16
(
)
(
)
[
]
log
=
(EQ. 2)
A
A) INPUT SIGNAL
C) THRESHOLD
B) RECTIFIED SIGNAL
D) ACCUMULATOR INPUTS
E) DETECTOR OUTPUT
A
A
A
A
A
F) CLOSED LOOP STEADY STATE
(CONSTANT INPUT)
FIGURE 11. SIGNAL PROCESSING WITHIN LEVEL DETECTOR
F
C
f
IN
* N
2
32
(
)
,
=
(EQ. 3)
N
INT F
C
2
32
F
IN
×
]
HEX
,
=
(EQ. 3A)
HSP50214
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