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參數(shù)資料
| 型號： | HSP50214VC |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Programmable Downconverter |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP120 |
| 封裝： | MQFP-120 |
| 文件頁數(shù)： | 26/54頁 |
| 文件大?。?/td> | 395K |
| 代理商： | HSP50214VC |
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26
Frequency Discriminator
The discriminator block delays phase from the Cartesian to
Polar section and subtracts it from the latest sample. This
delay and subtract can be modeled as a programmable
delay comb filter. The output of the filter is d
θ
/dt, or fre-
quency. The transfer function of the discriminator is set by
where D is the programmable discriminator delay expressed
in number of sample clock delays. The discriminator output
frequency is then filtered with a programmable FIR filter. The
block diagram of the Frequency Discriminator is shown in
Figure 29.
The range of delay in the discriminator is from 1 to 8 sam-
ples. Modulo 2
π
subtraction eliminates rollover problems in
the subtraction at 2
π
. The alias free discriminator frequency
range is given by:
where D is the discriminator delay defined in Equation 21
(1 < D < 8), FSAMP
OUT
is the Discriminator FIR filter output
sample rate and CW is the desired center frequency. When
the phase multiplier is set to a value other than 2
0
, the dis-
criminator range is reduced proportionally. The phase multi-
plier can be 1, 2, 4 or 8 (2
0
to 2
3
). Thus, a multiply of 2
1
reduces the range by 2, a multiply of 2
2
reduces the range
by 4, and a multiply of 2
3
reduces the range by 8.
The FIR filter can be configured with up to 63 symmetric taps
and up to 32 asymmetric taps. In the symmetric mode, the
FIR can be configured for even or odd symmetry, as well as
with an even or odd number of filter taps. Decimation is pro-
vided to allow more processing time for longer (i.e., more
taps) filter structures.
The discriminator input is 18 bits, and the output is rounded
asymmetrically to 16 bits. The phase into the discriminator
can be multiplied by 2
0
, 2
1
, 2
2
, or 2
3
(modulo 2
π
) to remove
PSK data modulation. All programmable parameters for the
Frequency Discriminator are set in Control Word 17. Bits 15
and 16 are the phase multiplier which represents the shift
applied to the input phase. For CW, the multiply should equal
2
0
, (00). For BPSK, QPSK, and 8PSK, the multiply should
equal 2
1
, (01); 2
2
, (10); or 2
3
, (11); respectively. Bit 14 is
used to enable or disable the discriminator. Bits 11-13 set
the decimation in the programmable FIR filter. Bit 10 sets the
filter symmetry type as either odd or even, bit 9 sets whether
the filter is asymmetric or symmetric, and bits 3-8 set the
number of FIR filter taps. Bits 0-2 set the number of delays in
the frequency discriminator.
Output Section
The output section routes the 7 types of processed signals to
output pins in three basic modes. These basic modes are:
Parallel Direct Output, Serial Direct Output, and the Buffer
RAM Output. The Serial and Parallel Direct Output modes
were designed to output data strobes and “real time” continu-
ous streams of data. The Buffer RAM Output mode outputs
data upon receipt of an asynchronous request from an exter-
nal DSP processor or other baseband processing engine. The
use of the interrupt signal from the Programmable Down Con-
verter in conjunction with the request strobes from the control-
ler ensures that data is transferred only when both the
controller and the Programmable Down Converter are ready.
The Buffer RAM output can be operated in a First In First Out
(FIFO) or SNAPSHOT mode with the data output either via
the 8-bit processor interface or a 16-bit processor interface.
TABLE 12. MAG/PHASE ACCURACY vs CLOCK CYCLES
CLOCKS
MAGNITUDE
ERROR
(% f
S
)
PHASE
ERROR
(DEG.)
PHASE
ERROR
(% f
S
)
6
0.065
3.5
2
7
0.016
1.8
1
8
0.004
0.9
0.5
9
<0.004
0.45
0.25
10
<0.004
0.22
0.12
11
<0.004
0.11
0.062
12
<0.004
0.056
0.03
13
<0.004
0.028
0.016
14
<0.004
0.014
0.008
15
<0.004
0.007
0.004
16
<0.004
0.0035
0.002
17
<0.004
0.00175
0.001
Assumes
±
180
o
= f
S
.
(EQ. 21)
H z
1
Z
D
–
–
=
(EQ. 22)
Range
FREQDISC
CW
F
±
SAMPOUT
D
1
+
(
)
;
=
+
DELAY
(1-8)
-
63-TAP
FIR
FILTER
PHASE INPUT
PHASE MULTIPLIER
DISCRIMINATOR DELAY
DISCRIMINATOR EN
DISC. FIR DECIMATION
FIR SYMMETRY TYPE
FIR SYMMETRY
FIR TAPS
FIR COEFFICIENTS
FREQ(15:0)
Controlled via microprocessor interface.
FIGURE 29. FREQUENCY DISCRIMINATOR BLOCK DIAGRAM
+
HSP50214
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50214VI | Programmable Downconverter |
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| HSP50215VC | Digital UpConverter |
| HSP50215VI | Digital UpConverter |
| HSP50215EVAL | DSP Modulator Evaluation Board |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215EVAL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215VC | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter |
| HSP50215VI | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter |
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