參數(shù)資料
型號： HSP50214VC
廠商： INTERSIL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Programmable Downconverter
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP120
封裝： MQFP-120
文件頁數(shù)： 16/54頁
文件大?。?/td> 395K
代理商： HSP50214VC
16
Depending on the number of halfbands used, PROCCLK
must operate a some minimum rate above the input sample
rate, F
S
, to the halfband. This relationship depends on the
number of multiplies for each of the halfband filter stages.
The filter calculations take 3, 4, 5, 6, and 7 multiplies per
input for HB1, HB2, HB3, HB4, and HB5 respectively. If we
keep the assumption that f
S
is the input sampling frequency,
then Equation 10 shows the minimum ratio needed.
f
PROCCLK
/f
S
≥
([(7)(HB5)(2
HB5
)+
(6)(HB4)(2
(HB4 + HB5)
)+
(5)(HB3)(2
(HB3+HB4+HB5)
)+
(4)(HB2)(2
(HB2+HB3+ HB4+HB5)
)+
(3)(HB1)(2
(HB1+HB2+HB3+HB4+HB5)
)]/2
T
(EQ. 10)
where:
HB1 = 1 if this section is selected and 0 if it is bypassed;
HB2 = 1 if this section is selected and 0 if it is bypassed;
HB3 = 1 if this section is selected and 0 if it is bypassed;
HB4 = 1 if this section is selected and 0 if it is bypassed;
HB5 = 1 if this section is selected and 0 if it is bypassed;
T = number of Halfband Filters Selected. The range for T is
from 0 to 5.
Examples of PROCCLK Rate Calculations
Suppose we enable HB1, HB3, and HB5. Using Figure 16,
HB1= 1, HB3 = 1, and HB5 = 1. Since stage 2 and stage 4
are not used, HB2 and HB4 = 0. PROCCLK must operate
faster than (7x2+5x4+3x8)/8 = 7.25 times faster than f
S
.
If all five halfbands are used, then PROCCLK must operate at
(7x2+6x4+5x8+4x16+3x32)/32 = 7.4375 times faster than f
S
.
TABLE 4. HALFBAND FILTER COEFFICIENTS
COEFFICIENTS
HALFBAND #1
HALFBAND #2
HALFBAND #3
HALFBAND #4
HALFBAND #5
C0
- 0.031303406
0.005929947
-0.00130558
-0.000378609
-0.000347137
C1
0.000000000
0.000000000
-0.000000000
-0.000000000
-0.000000000
C2
0.281280518
-0.049036026
-0.012379646
-0.003810883
-0.00251317
C3
0.499954224
0.000000000
-0.000000000
-0.000000000
-0.000000000
C4
0.281280518
0.29309082
-0.06055069
-0.019245148
-0.010158539
C5
0.000000000
0.499969482
-0.000000000
-0.000000000
-0.000000000
C6
- 0.031303406
0.29309082
-0.299453735
-0.069904327
-0.03055191
C7
0.000000000
-0.499954224
-0.000000000
-0.000000000
C8
-0.049036026
-0.299453735
-0.304092407
-0.081981659
C9
0.000000000
-0.000000000
-0.500000000
-0.000000000
C10
0.005929947
-0.06055069
-0.304092407
-0.309417725
C11
-0.000000000
0.000000000
-0.500000000
C12
-0.012379646
-0.069904327
-0.309417725
C13
-0.000000000
-0.000000000
-0.000000000
C14
-0.00130558
-0.019245148
-0.081981659
C15
-0.000000000
-0.000000000
C16
-0.003810883
-0.03055191
C17
-0.000000000
-0.000000000
C18
-0.000378609
-0.010158539
C19
-0.000000000
C20
-0.00251317
C21
-0.000000000
C22
-0.000347137
NOTE: While Halfband filters are typically selected starting with the last stage in the filter chain to give the maximum alias free
bandwidth, a higher throughput rate may be obtained using other filter combinations. See Application Note 9720, “Calculat-
ing Maximum Processing Rates of the PDC”.
HSP50214
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HSP50215EVAL 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board
HSP50215VC 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter
HSP50215VI 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital UpConverter
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