參數(shù)資料
型號(hào)： HSP50214VC
廠商： INTERSIL CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Programmable Downconverter
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP120
封裝： MQFP-120
文件頁數(shù)： 36/54頁
文件大?。?/td> 395K
代理商： HSP50214VC
36
Suppose a (0018D038)H needs to be loaded into control word
0, then Table 20 details the steps to be taken.
Microprocessor Read Section
The microprocessor read uses both read and write proce-
dures to obtain data from the PDC. A write must be done to
location 5 to select the source of data to be read. The read
source is determined by the value placed on the lower three
bits of C(7:0). The output from a particular read code is
selected using a read address placed on A(2:0). The output
is sent to C(7:0) on the falling edge of RD.
If the Read Address is equal to 111, the Read Code is
ignored, and the status bits shown in Table 22 in the Output
Section is sent to C(7:0). This state was provided so that the
user could obtain the status bits quickly.
Refer to the timing diagram in Figure 43. Suppose the input
level detector has a hex value of (321AF5)H, then Table 21
details the steps to be taken.
TABLE 19. DEFINITION OF ADDRESS MAP
A2-0
REGISTER DESCRIPTION
0
Holding Register 0. Transfers to bits 7-0 of the 32-bit des-
tination register. Bit 0 is the LSB of the 32-bit register.
1
Holding Register 1. Transfers to bits 15-8 of a 32-bit desti-
nation register.
2
Holding Register 2. Transfers to bits 23-16 of a 32-bit des-
tination register.
3
Holding Register 3. Transfers to bits 31-24 of a 32-bit des-
tination register. Bit 31 is the MSB of the 32-bit register.
4
This is the destination address register. On the fourth CLK
following a write to this register, the contents of the holding
registers are transferred to the destination register. All 8
bits written to this register are decoded into the destination
register address. The configuration destination address
map is given in the tables in the Control Word section.
5
Selects data source for reading. See Microprocessor Read
Section.
TABLE 20. EXAMPLE PROCESSOR WRITE SEQUENCE
STEP
A(2:0)
C(7:0)
COMMENT
1
000
0011 1000
Loads 38 into master register
(7:0) on rising edge of WR
2
001
1101 0000
Loads D0 into master register
(15:8) on rising edge of WR
3
010
0001 1000
Loads 18 into master register
(23:16) on rising edge of WR
4
011
0000 0000
Loads 00 into master register
(31:24) on rising edge of WR
5
100
0000 0000
Load “0018D038” into Configu-
ration Control Register 0
6
Wait 4 CLKS
WR
0
1
2
3
4
LOAD
CONFIGURATION
DATA
LOAD ADDRESS OF
TARGET CONTROL
REGISTER AND
WAIT 4 CLKs
2
CLK =
A2-0
C7-0
LOAD NEXT
CONFIG-
URATION
REGISTER
0
1
2
3
4
(PROCCLK,
CLKIN)
FIGURE 42. LOADING THE CONTROL REGISTERS WITH
32-BIT CONTROL WORDS
LSB
MSB ADD
TABLE 21. PROCESSOR READ SEQUENCE (INPUT LEVEL
SETECTOR)
STEP
A(2:0)
C(7:0)
COMMENT
1
101
100
Write Read Code, 100 to
Address 5, WR pulled high to
generate rising edge.
2
000
1111 1000
(F4)H
Drop RD low, Read AGC
LSB
3
001
0001 1010
(1A)H
Pull RD high, then drop low,
Read AGC NLSB
4
010
0011 0010
(32)H
Pull RD high, then drop low,
Read AGC MSB
WR
LOAD ADDRESS
OF TARGET
CONTROL REGISTER
PROCLK
A2-0
C7-0
ASSERT RD
TO ENABLE DATA
OUTPUT ON C0-7
READ CODE C(2:0)
THREE-STATE
INPUT BUS
RD
5
FIGURE 43. READING THE CONTROL REGISTERS USING A
LATCH CODE EQUAL TO A 5, A READ ADDRESS
AND A READ CODE
READ ADDRESS
OUTPUT DATA C(7:0)
HSP50214
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