參數(shù)資料
型號(hào)： GS4910BCNE3
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 88/113頁(yè)
文件大小： 1017K
代理商： GS4910BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
88 of 113
H_Feedback_Divide
29h-28h
31-0
In the internal video genlock block, this register defines
the numerator of the divide ratio.
This register may be programmed to manually genlock
the output to the input reference.
The default value of this register will vary depending on
the output video standard selected.
Address 28h = bits 15-0
Address 29h = bits 31-16
Reference:
Section 3.6.2.1 on page 54
R/W
–
H_Reference_Divide
2Bh-2Ah
31-0
In the internal video genlock block, this register defines
the denominator of the divide ratio.
This register may be programmed to manually genlock
the output to the input reference.
The default value of this register will vary depending on
the output video standard selected.
Address 2Ah = bits 15-0
Address 2Bh = bits 31-16
Reference:
Section 3.6.2.1 on page 54
R/W
–
PCLK1_Phase/Divide
2Ch
15-7
Reserved. Set these bits to zero when writing to 2Ch.
–
–
2Ch
6
Current_P1 - selects the current drive capability of the
PCLK1 pin. Set this bit HIGH for high current drive.
Otherwise, the current drive will be low.
NOTE: The current drive should be set high if PCLK1 is
greater than 100MHz.
Reference:
Section 3.7.1 on page 61
R/W
0
2Ch
5-2
PCLK1_Phase - adjusts the output phase of the PCLK1
clock with respect to the timing output pins. Phase is
delayed in 700ps (nominal) increments as shown in
Table 3-6
.
Reference:
Section 3.7.1 on page 61
R/W
0
2Ch
1
Divide_By_4 - set this bit HIGH to divide the output
PCLK1 by four.
NOTE: Setting this bit and bit 0 simultaneously HIGH
will hold the PCLK1 pin LOW.
Reference:
Section 3.7.1 on page 61
R/W
0
2Ch
0
Divide_By_2 - set this bit HIGH to divide the output
PCLK1 by two.
NOTE: Setting this bit and bit 1 simultaneously HIGH
will hold the PCLK1 pin LOW.
Reference:
Section 3.7.1 on page 61
R/W
0
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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參數(shù)描述
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