參數(shù)資料
型號(hào)： GS4910BCNE3
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 91/113頁(yè)
文件大?。?/td> 1017K
代理商： GS4910BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
91 of 113
N
a
(GS4911B only)
34h-33h
31-0
A non-zero number programmed in this register defines
the numerator for the ratio of the audio clock to the
27MHz reference.
NOTE: Once this register is programmed, it must be
updated using bit 6 of register 31h.
The default value of this register will vary depending on
the output audio rate selected.
Address 33h = bits 15-0
Address 34h = bits 31-16
Reference:
Section 3.9.2 on page 73
.
R/W
–
D
a
(GS4911B only)
36h-35h
31-0
A non-zero number programmed in this register defines
the denominator for the ratio of the audio clock to the
27MHz reference.
NOTE: Once this register is programmed, it must be
updated using bit 6 of register 31h.
The default value of this register will vary depending on
the output audio rate selected.
Address 35h = bits 15-0
Address 36h = bits 31-16
Reference:
Section 3.9.2 on page 73
.
R/W
–
RSVD
37h - 38h
–
Reserved.
–
–
Audio_Cap_Genlock
(GS4911B only)
39h
15-6
Reserved. Set these bits to zero when writing to 39h.
–
–
39h
5-0
Control signal to adjust loop bandwidth of audio genlock
block.
The value programmed in this register must be between
10 and Audio_Res_Genlock - 21.
The default value of this register will depend on the
fundamental sampling frequency selected.
Reference:
Section 3.6.4 on page 58
R/W
–
Audio_Res_Genlock
(GS4911B only)
3Ah
15-6
Reserved. Set these bits to zero when writing to 3Ah.
–
–
3Ah
5-0
Control signal to adjust loop bandwidth of audio genlock
block.
The value programmed in this register must be between
32 and 42.
The default value of this register will depend on the
fundamental sampling frequency selected.
Reference:
Section 3.6.4 on page 58
R/W
–
A_Feedback_Divide
(GS4911B only)
3Ch-3Bh
31-0
In the internal audio genlock block, this register defines
the numerator of the divide ratio.
This register may be programmed to manually genlock
the audio clock to the video clock.
The default value of this register will vary depending on
the output video standard selected.
Address 3Bh = bits 15-0
Address 3Ch = bits 31-16
Reference:
Section 3.6.2.2 on page 56
R/W
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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參數(shù)描述
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