參數(shù)資料
型號(hào)： GS4910BCNE3
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 14/113頁(yè)
文件大?。?/td> 1017K
代理商： GS4910BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
14 of 113
36
TIMING_OUT_2
Synchronous
with PCLK1 ~
PCLK3
Output
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See
Section 1.5 on page 25
for signal descriptions.
NOTE: Default output is H blanking.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
37
TIMING_OUT_3
Synchronous
with PCLK1 ~
PCLK3
Output
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See
Section 1.5 on page 25
for signal descriptions.
NOTE: Default output is V Sync.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
39
TIMING_OUT_4
Synchronous
with PCLK1 ~
PCLK3
Output
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See
Section 1.5 on page 25
for signal descriptions.
NOTE: Default output is V blanking.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
40
TIMING_OUT_5
Synchronous
with PCLK1 ~
PCLK3
Output
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See
Section 1.5 on page 25
for signal descriptions.
NOTE: Default output is F Sync.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料
PDF描述
GS4911B HD/SD/Graphics Clock and Timing Generator with GENLOCK
GS4911BCNE3 HD/SD/Graphics Clock and Timing Generator with GENLOCK
GS4915 CONN,S/R,8 POS,254C-08-1, CLOSED END STRAIN RELIEF COVER
GS6332 3 Pin, Low-Power, P Reset Circuits
GS6332UR15D1 3 Pin, Low-Power, P Reset Circuits
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS4911ACNE3 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
GS4911B 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK
GS4911B_09 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK
GS4911BCNE3 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
GS4915 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*