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參數(shù)資料
| 型號： | GS4910BCNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| 中文描述： | 高清/標清/圖形時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 44/113頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | GS4910BCNE3 |
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GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
44 of 113
Timing for Graphics Formats
The GS4911B/GS4910B is pre-programmed to recognize the timing for 16
different graphics formats presented to the input reference pins. These graphic
formats are described in
Section 1.4 on page 20
.
The supported graphics standards are all progressive, and do not use the FSYNC
signal. Therefore, FSYNC should be held LOW by the application layer. The VESA
formats supported have a 0.5% frequency tolerance.
VSYNC transitions are typically co-timed with the leading edge of HSYNC. The
duration and polarity of these signals for each format is listed in
Table 1-2
.
NOTE: The user must ensure that the input HSYNC polarity for VID_STD [5:0] = 47
and 49 – 54 be active LOW.
3.4.2 10FID
The 10FID input is a reset pin, which can be used to reset the divider for the 10FID
output signal. In the GS4911B, the 10FID input pin will also reset the divider for the
AFS output signal. This default setting may be modified using the Audio_Control
register of the host interface (see
Section 3.12.3 on page 79
).
The GS4911B will reset the phase of the audio clocks to the leading edge of the H
Sync output on line 1 of every output frame in which the 10FID input is HIGH. This
enables the user to reset the phase of the dividers when generating custom signals
via the host interface (see
Section 3.7.2.1 on page 65
).
If the input reference format does not include a 10 Field ID signal, the external
10FID input pin should be held LOW.
The timing of the 10FID input signal is shown in
Figure 3-5
.
Figure 3-5: 10FID Input Timing
10FID Input
Horizontal Sync Input
Total Line
Line 1, Frame 1 every 'n' frames
Line 1 every n frames where:
n = 5 @ 29.97 fps, 30 fps
n = 10 @ 59.94 fps, 60 fps
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS4911B | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4915 | CONN,S/R,8 POS,254C-08-1, CLOSED END STRAIN RELIEF COVER |
| GS6332 | 3 Pin, Low-Power, P Reset Circuits |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4911ACNE3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS4911B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4915 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
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