參數(shù)資料
型號(hào)： GS4910BCNE3
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 82/113頁(yè)
文件大小： 1017K
代理商： GS4910BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
82 of 113
Genlock_Control
16h
15-7
Reserved. Set these bits to zero when writing to 16h.
–
–
16h
6
Update_Custom_V_Clock - this bit is used to update the
custom video clock parameters programmed in registers
20h to 23h of the host interface. All non-zero
parameters in these registers will be updated via a LOW
to HIGH transition on this bit.
This bit is also used to enable the Extended Audio Mode
of the device.
R/W
0
16h
5
Genlock_From_Host - set this bit HIGH to enable video
genlock control via the Host Interface instead of the
external GENLOCK pin (see bit 0 of this register).
Reference:
Section 3.2 on page 36
R/W
0
16h
4
F_Lock_Mask - if this bit is set HIGH, the
GS4911B/GS4910B will ignore the status of F_Lock (bit
4 of register 15h) when determining the status of
Reference_Lock (bit 5 of register 15h).
Reference:
Section 3.6.1 on page 50
R/W
0
16h
3
V_Lock_Mask - if this bit is set HIGH, the
GS4911B/GS4910B will ignore the status of V_Lock (bit
3 of register 15h) when determining the status of
Reference_Lock (bit 5 of register 15h).
Reference:
Section 3.6.1 on page 50
R/W
0
16h
2
H_Lock_Mask - if this bit is set HIGH, the
GS4911B/GS4910B will ignore the status of H_Lock (bit
2 of register 15h) when determining the status of
Reference_Lock (bit 5 of register 15h).
Reference:
Section 3.6.1 on page 50
R/W
0
16h
1
Drift_Crash - when this bit is set HIGH, the generated
video clock will drift lock to a new input reference rather
than crash lock.
Reference:
Section 3.6.3 on page 58
R/W
0
16h
0
GENLOCK - this bit may be used instead of the external
pin to Genlock the output video format to the input
reference. This bit will be ignored if bit 5 of this register
is LOW.
Reference:
Section 3.2 on page 36
R/W
0
Output_H_Reset
17h
15-0
When the output is genlocked to the input, the input
reference is used to reset the line-based counter
controlling the generated timing output signals.
Programming this register to a non-zero value will
over-ride the internal pixel-based counter. The counter
reset will occur every Output_H_Reset lines instead of
on a frame basis.
This register is programmed when manually
programming the internal video genlock block.
The default value of this register will vary depending on
the output video standard selected.
Reference:
Section 3.6.2 on page 54
R/W
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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參數(shù)描述
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