參數(shù)資料
型號(hào)： GS4910BCNE3
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁數(shù)： 79/113頁
文件大?。?/td> 1017K
代理商： GS4910BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
79 of 113
3.12.3 Configuration and Status Registers
Table 3-13
summarizes the GS4911B/GS4910B's internal status and configuration
registers.
All registers are available to the host via the GSPI and are all individually
addressable.
Table 3-13: Configuration and Status Registers
Register Name
Address
Bit
Description
R/W
Default
RSVD
00h - 09h
–
Reserved.
–
–
H_Period
0Ah
15-0
Contains the number of 27MHz pulses in the input H
Sync period. This register is set by the Reference
Format Detector block using the H Sync signal present
on the external HSYNC input pin.
NOTE: If the reference is removed this register will
remain unchanged until a new reference with a different
HSYNC period is applied.
Reference:
Section 3.5.1 on page 45
R
N/A
H_16_Period
0Bh
15-0
Contains the number of 27MHz pulses in 16 H Sync
periods. This register is set by the Reference Format
Detector block using the H Sync signal present on the
external HSYNC input pin. It is useful for 1/1.001 data
detection.
NOTE: If the reference is removed this register will
remain unchanged until a new reference with a different
HSYNC period is applied.
Reference:
Section 3.5.1 on page 45
R
N/A
V_Lines
0Ch
15-0
Contains the number of H Sync periods in the input V
Sync interval. This register is set by the Reference
Format Detector block using the signals present on the
external HSYNC and VSYNC input pins.
NOTE: If the reference is removed this register will
remain unchanged until a new reference with a different
VSYNC period is applied.
Reference:
Section 3.5.1 on page 45
R
N/A
V_2_Lines
0Dh
15-0
Contains the number of H Sync periods in 2 V Sync
intervals. This register is set by the Reference Format
Detector block using the signals present on the external
HSYNC and VSYNC input pins.
NOTE: If the reference is removed this register will
remain unchanged until a new reference with a different
VSYNC period is applied.
Reference:
Section 3.5.1 on page 45
R
N/A
F_Lines
0Eh
15-0
Contains the number of H Sync periods in the input F
Sync interval. This register is set by the Reference
Format Detector block using the signals present on the
external HSYNC and FSYNC input pins.
NOTE: If the reference is removed this register will
remain unchanged until a new reference is applied. If
the new reference does not include an FSYNC pulse,
this register will be set to zero.
Reference:
Section 3.5.1 on page 45
R
N/A
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