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參數(shù)資料
| 型號： | GS4910BCNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| 中文描述： | 高清/標清/圖形時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 49/113頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | GS4910BCNE3 |
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GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
49 of 113
Acquisition of a New Reference
When a new reference is applied, the device continues to operate in Freeze mode
while the reference format detector checks for validity as described in
Section 3.5.2
on page 45
. Once validity is detected, the REF_LOST pin is set LOW.
Assuming GENLOCK is LOW, the device will then attempt to genlock the selected
output clock and timing signals to the new input reference. If the output can be
automatically genlocked to the new input reference, LOCK_LOST will go LOW and
the device will re-enter Genlock mode. Otherwise, the LOCK_LOST pin will remain
HIGH and the device will enter Free Run mode.
If VID_STD[5:0] = 63 when the new reference is applied, the device will send the
detected timing parameters to the clock synthesis and timing generator blocks. The
new output format will start being generated during the first reference V period after
the reference format has been reliably established. The LOCK_LOST pin will go
LOW and the device will re-enter Genlock mode.
3.5.4 Allowable Frequency Drift on the Reference
By default, the frequency of the reference H pulse on HSYNC may drift from its
expected value by approximately +/- 0.2% before the internal video PLL loses lock.
This tolerance may be adjusted using the Max_Ref_Delta register at address 1Eh
of the host interface.
The encoding scheme is shown in
Table 3-3
. The default value of the register is Bh.
NOTE: Regardless of the setting of this register, the device will always differentiate
between 59.94Hz and 60Hz reference standards.
Table 3-3: Max_Ref_Delta Encoding Scheme
Register
Setting
Maximum Allowable
Frequency Drift
Register
Setting
Maximum Allowable
Frequency Drift
0h
+/- 2
-20
8h
+/- 2
-12
1h
+/- 2
-19
9h
+/- 2
-11
2h
+/- 2
-18
Ah
+/- 2
-10
3h
+/- 2
-17
Bh
+/- 2
-9
4h
+/- 2
-16
Ch
+/- 2
-8
5h
+/- 2
-15
Dh
+/- 2
-7
6h
+/- 2
-14
Eh
+/- 2
-6
7h
+/- 2
-13
Fh
+/- 2
-5
The maximum allowable frequency drift is measured as a fraction of the frequency of the reference
H pulse.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS4911ACNE3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS4911B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4915 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
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