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參數(shù)資料
| 型號： | GS4910BCNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| 中文描述： | 高清/標清/圖形時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 48/113頁 |
| 文件大小： | 1017K |
| 代理商： | GS4910BCNE3 |
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GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
48 of 113
NOTE 2: When locking the
“f/1.001”
HD output standards to the SD input reference
standards 3, 5, 7, or 9, or vice versa, there may be a random phase difference
between the input VSYNC and output V Sync signals occuring each time the input
reference is removed and re-applied. This will affect all line-based timing outputs.
For cases where the user must manually video genlock the device, the problem will
occur whenever the value programmed for H_Reference_Divide (registers 2B-2A
h
)
is greater than 1. The user may reset the line-based counters after the reference is
re-applied without disrupting the pixel or audio clocks by toggling bit 15 of register
address 83h in the host interface. This will cause the input VSYNC and line-based
timing output signals to take on their default timing relationship, as described in
Note 3 of
Section 3.2.1.1 on page 37
.
Re-acquisition of the Same Reference
Upon re-application of the reference signal, the device checks whether the
reference has drifted more than +/- 2us from its expected location by comparing
the current relative position of the H pulses with the previous position, over a
16-line interval. If the reference returns with the H pulses in the expected location
+/- 2us, the PLL will drift lock and the clock generator will continue to operate
without a glitch. The REF_LOST and LOCK_LOST pins will be set back LOW.
If the reference returns with the H pulses outside the +/- 2us window, the device
will crash lock the output timing to the new input phase. The principles of crash lock
and drift lock are described in
Section 3.6.3 on page 58
.
NOTE: To resume proper genlock operation upon re-application of the reference
signal, the user must implement the following register manipulation every time the
reference is removed and re-applied:
1. Read the value contained in register address 24h
2. Clear the Run_Window bits [2:0] of register 24h
3. Re-write the value read in step 1 to register address 24h.
This procedure will force the device to lock to the reference as described above,
but will maintain the flywheeling capability of the GS4911B/GS4910B should a
single missing H pulse occur in the genlocked state.
To avoid the above procedure, the user may choose to clear the Run_Window bits
[2:0] of register address 24h upon power-up or reset. However, this will disable the
flywheeling feature of the device that allows it to maintain genlock through one
missing input H pulse.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4911ACNE3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS4911B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4915 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
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