參數(shù)資料
型號: GS4910BCNE3
廠商: Gennum Corporation
英文描述: HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述: 高清/標清/圖形時鐘和定時發(fā)生器鎖相
文件頁數(shù): 102/113頁
文件大小: 1017K
代理商: GS4910BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
102 of 113
H_Start_4
66h
15-0
The value programmed in this register indicates the
pixel start point for the leading edge of the
user-programmed H Sync signal USER4_H.
NOTE: The value programmed in this register must be
less than the value programmed in H_Stop_4.
Reference:
Section 3.8.3
R/W
0
H_Stop_4
67h
15-0
The value programmed in this register indicates the
pixel end point for the trailing edge of the
user-programmed H Sync signal USER4_H.
NOTE: The value programmed in this register must not
exceed the maximum number of clock periods per line
of the outgoing standard.
Reference:
Section 3.8.3 on page 69
R/W
0
V_Start_4
68h
15
Reserved. Set this bit to zero when writing to 68h.
68h
14-0
The value programmed in this register indicates the start
line number of the leading edge of the
user-programmed V Sync signal USER4_V. For
interlaced output standards, this value corresponds to
the odd field line number.
NOTE: The value programmed in this register must be
less than the value programmed in V_Stop_4.
Reference:
Section 3.8.3 on page 69
R/W
0
V_Stop_4
69h
15
Reserved. Set this bit to zero when writing to 69h.
69h
14-0
The value programmed in this register indicates the end
line number of the trailing edge of the user-programmed
V Sync signal USER4_V. For interlaced output
standards, this value corresponds to the odd field line
number.
NOTE: The value programmed in this register must not
exceed the maximum number of lines per field of the
outgoing standard.
Reference:
Section 3.8.3 on page 69
R/W
0
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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