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| 型號： | GS4910BCNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| 中文描述： | 高清/標(biāo)清/圖形時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 74/113頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | GS4910BCNE3 |
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GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
74 of 113
3.10 Custom Output Timing Signal Generation
In addition to the devices’s pre-programmed output timing signals, the user may
also build their own custom timing signals. This is achieved by setting
VID_STD[5:0] = 62 and programming designated host registers.
When programming custom output timing signals, the user must define the pixel,
line, and field/frame timing parameters using registers 4Eh to 55h of the host
interface (see
Figure 3-12
). For all custom formats, the VSync output will start on
line 1 of the video field. The user may delay the VSync pulse to any line using the
V_Offset register (see Section 3.2.1.1).
When the user sets VID_STD[5:0] = 62, registers 4Eh to 55h will become
read/write configurable and the device will initially continue to output timing signals
based on the video format previously selected. Once the user has programmed all
eight custom timing registers, generation of the new timing signals will begin.
The frequency of the video clock will remain as previously selected unless
otherwise modified as described in
Section 3.9.1 on page 72
.
NOTE: If VID_STD[5:0] = 62 on power-up, the initial output timing signals will be
set to the internal default timing of the chip until the user programs 4Eh to 55h.
Figure 3-12: Custom Timing Parameters
3.10.1 Custom Input Reference
As explained in
Section 3.5.2 on page 45
, when VID_STD[5:0] = 62, the device will
only verify that a stable signal with a period of less than 2.4ms is present on the
HSYNC input pin before attempting to genlock. Therefore, in addition to
programming custom output timing signals, the user may genlock the output timing
signals to a custom reference pulse applied to HSYNC. In this case the user is
required to manually program the video genlock block (see
Section 3.6.2.1 on
page 54
).
H Blanking
H Sync
Clocks_Per_Line (4Eh)
Clocks_Per_Hsync (4Fh)
Hsync_To_SAV (50h)
Hsync_To_EAV (51h)
Lines_Per_Field (52h)
Lines_Per_Vsync (53h)
Vsync_To_First_Active_Line (54h)
Vsync_To_Last_Active_Line (55h)
V Blanking
V Sync
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4911ACNE3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS4911B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4915 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
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