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| 型號： | GS4910BCNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| 中文描述： | 高清/標(biāo)清/圖形時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 89/113頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | GS4910BCNE3 |
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GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
89 of 113
PCLK2_Phase/Divide
2Dh
15-7
Reserved. Set these bits to zero when writing to 2Dh.
–
–
2Dh
6
Current_P2 - selects the current drive capability of the
PCLK2 pin. Set this bit HIGH for high current drive.
Otherwise, the current drive will be low.
NOTE: The current drive should be set high if PCLK2 is
greater than 100MHz.
Reference:
Section 3.7.1 on page 61
R/W
0
2Dh
5-2
PCLK2_Phase - adjusts the output phase of the PCLK2
clock with respect to the timing output pins. Phase is
delayed in 700ps (nominal) increments as shown in
Table 3-6
.
Reference:
Section 3.7.1 on page 61
R/W
0
2Dh
1
Divide_By_4 - set this bit HIGH to divide the output
PCLK2 by four.
NOTE: Setting this bit and bit 0 simultaneously HIGH
will hold the PCLK2 pin LOW.
Reference:
Section 3.7.1 on page 61
R/W
0
2Dh
0
Divide_By_2 - set this bit HIGH to divide the output
PCLK2 by two.
NOTE: Setting this bit and bit 1 simultaneously HIGH
will hold the PCLK2 pin LOW.
Reference:
Section 3.7.1 on page 61
R/W
0
PCLK3_Phase/Divide
2Eh
15-6
Reserved. Set these bits to zero when writing to 2Eh.
–
–
2Eh
5-2
PCLK3_Phase - adjusts the output phase of the
PCLK3/PCLK3 clock with respect to the timing output
pins. Phase is delayed in 700ps (nominal) increments
as shown in
Table 3-6
.
Reference:
Section 3.7.1 on page 61
R/W
0
2Eh
1
Divide_By_4 - set this bit HIGH to divide the output
PCLK3/PCLK3 by four.
Setting this bit and bit 0 simultaneously HIGH will give
the full rate video clock on the PCLK3 / PCLK3 pins.
Reference:
Section 3.7.1 on page 61
R/W
0
2Eh
0
Divide_By_2 - set this bit HIGH to divide the output
PCLK3/PCLK3 by two.
Setting this bit and bit 1 simultaneously HIGH will give
the full rate video clock on the PCLK3 / PCLK3 pins.
Reference:
Section 3.7.1 on page 61
R/W
0
PCLK3_Tristate
2Fh
15-2
Reserved. Set these bits to zero when writing to 2Fh.
–
–
2Fh
1-0
Set these bits to 11b to tristate the PCLK3 / PCLK3 pins.
Reference:
Section 3.7.1 on page 61
R/W
00b
RSVD
2Fh - 30h
–
Reserved.
–
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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| GS4911BCNE3 | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4911ACNE3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS4911B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4915 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
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