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參數(shù)資料
| 型號： | GS4910BCNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| 中文描述： | 高清/標清/圖形時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 87/113頁 |
| 文件大小： | 1017K |
| 代理商： | GS4910BCNE3 |
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GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
87 of 113
Constcf_Genlock
24h
15-8
Crash_Time - controls the crash lock period of video
PLL locking process. This time contributes to the total
PLL Lock Time given in the AC Characteristics Table.
The time of the crash process in H reference periods is
determined by [Crash_Time x 4] + 1.
The default value of these bits will vary depending on
the output video standard selected.
Reference:
Section 3.6.3 on page 58
R/W
–
24h
7-3
Lock_Lost_Threshold - controls the threshold of the lock
indication circuit. A larger value programmed in this
register can increase the stability of the LOCK_LOST
output signal when the input H reference signal is
subject to large amounts of low frequency jitter. A larger
value in this register will also increase the lock indication
time, although not the actual lock time of the device.
The default value of these bits will vary depending on
the output video standard selected.
R/W
–
24h
2-0
Run_Window - controls the output frequency error in the
case of a missing or mis-timed H reference transition.
The default value of this register allows the device to
maintain genlock through one missing input H pulse.
This feature can be disabled by programming
Run_Window = 000b. In this case, the device will
immediately react to any disturbance of the input H
signal.
The default value of these bits will vary depending on
the output video standard selected.
Reference:
Section 3.5.3 on page 47
R/W
–
RSVD
25h
–
Reserved.
–
–
Video_Cap_Genlock
26h
15-6
Reserved. Set these bits to zero when writing to 26h.
–
–
26h
5-0
Control signal to adjust loop bandwidth of video genlock
block.
The value programmed in this register must be between
10 and Video_Res_Genlock - 21.
The default value of this register will vary depending on
the output video standard selected.
Reference:
Section 3.6.4 on page 58
R/W
–
Video_Res_Genlock
27h
15-6
Reserved. Set these bits to zero when writing to 27h.
–
–
27h
5-0
Control signal to adjust loop bandwidth of video genlock
block.
The value programmed in this register must be between
32 and 42.
The default value of this register will vary depending on
the output video standard selected.
Reference:
Section 3.6.4 on page 58
R/W
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS4911ACNE3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS4911B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4915 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
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