參數(shù)資料
型號(hào)： GS4910BCNE3
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 83/113頁(yè)
文件大?。?/td> 1017K
代理商： GS4910BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
83 of 113
Output_FV_Reset
18h
15-0
When the output is genlocked to the input, the input
reference is used to reset the frame-based counter
controlling the generated timing output signals.
Programming this register to a non-zero value will
over-ride the internal frame-based counter. The counter
reset will occur every Output_FV_Reset input frames.
This register is programmed when manually
programming the internal video genlock block.
NOTE: Once this register is programmed, it must be
updated using register 19h.
The default value of this register will vary depending on
the output video standard selected.
Reference:
Section 3.6.2 on page 54
R/W
–
Frame_Divider_Reset
19h
15-2
Reserved. Set these bits to zero when writing to 19h.
–
–
19h
1
Ref_F_Sync - when Ref_F_Mode (bit 0 of 19h) is set
HIGH, this bit is used to initialize the frame-based
counter reset programmed in 18h.
The reset pulse is generated if this bit is pulsed (LOW to
HIGH to LOW) during the output frame immediately
prior to the frame the reset is to occur.
This register is programmed when manually
programming the internal video genlock block.
Reference:
Section 3.6.2 on page 54
R/W
0
19h
0
Ref_F_Mode - set this bit HIGH to initialize the
frame-based reset via the host interface (using bit 1
above).
Reference:
Section 3.6.2 on page 54
R/W
0
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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