
GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 71
Capacitance
CIDSEL
IDSEL Pin
Capacitance
8
pF
4
Lpin
Pin Inductance
20
nH
5
IOff
PME# input leakage
Vo
3.6 V
≦
Vcc off or
floating
-
1
μ
A
6
Notes:
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are
calculated to pull a floated network. Applications sensitive to static power utilization must assure that the
input buffer is conducting minimum current at this input voltage.
2. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK, SMBDAT, and SMBCLK) with
an exception granted to system board-only devices up to 16 pF in order to accommodate PGA packaging. This
would mean, in general, that components for add-in cards need to use alternatives to ceramic PGA packaging;
i.e., PQFP, SGA, etc. Pin capacitance for SMBCLK and SMBDAT is not specified; however, the maximum
capacitive load is specified for the add-in card in Section 8.2.5.
4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
5. This is a recommendation, not an absolute requirement. The actual value should be provided with the
component data sheet.
6. This input leakage is the maximum allowable leakage into the PME# open drain driver when power is
removed from Vcc of the component. This assumes that no event has occurred to cause the device to attempt
to assert PME#.
7.5 PCI Interface AC Specifications
Symbol
Parameter
Condition
Min.
Max
Units
Notes
0 < Vout
0.3Vcc
≦
-12Vcc
mA
1
0.3Vcc<Vout<0.9Vcc
-17.1(Vcc-Vout)
mA
1
Ioh(AC)
Switching
Current High
0.7Vcc < Vout < Vcc
Eqt'n C
1, 2
Vcc >Vout
0.6Vcc
≧
16Vcc
mA
1
0.6Vcc>Vout>0.1Vcc
26.7Vout
mA
1
Iol(AC)
Switching
Current Low
0.18Vcc>Vout>0
Eqt'n D
1, 2