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參數(shù)資料
| 型號： | GL9701 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | PCI ExpressTM to PCI Bridge |
| 中文描述： | 的PCI ExpressTM到PCI橋 |
| 文件頁數(shù)： | 70/75頁 |
| 文件大小： | 1077K |
| 代理商： | GL9701 |
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GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 70
is not the same as the mean. The jitter median describes the point in time where the number of jitter points on
either side is approximately equal as opposed to the averaged time value.
The RX UI recovered using the clock recovery function must be used as the reference for the eye diagram.
This parameter is measured with the equivalent of a zero jitter reference clock. The TRX-EYE measurement is
to be met at the target bit error rate. The TRX-EYE-MEDIAN-to-MAX-JITTER specification is to be met
using the compliance pattern at a sample size of 1,000,000 UI.
10. See the
PCI Express Jitter and BER
white paper for more details on the Rx-Eye measurement.
11. The Receiver input impedance shall result in a differential return loss greater than or equal to 10 dB with a
differential test input signal of no less than 200 mV (peak value, 400 mV differential peak to peak) swing
around ground applied to D+ and D- lines and a common mode return loss greater than or equal to 6 dB (no
bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to
all valid input levels. The reference impedance for return loss measurements for is 50
Ω
to ground for both
the D+ and D- line. Note that the series capacitors CTX is optional for the return loss measurement.
12. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state
of the LTSSM) there is a 5 ms transition time before Receiver termination values must be met on all
un-configured Lanes of a Port.
13. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is
asserted. This helps ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on
when it is not. This term must be measured at 200 mV above the RX ground.
7.4 PCI Interface DC Specifications
Symbol
Parameter
Condition
Min.
Max
Units
Notes
Vcc
Supply Voltage
3.0
3.6
V
Vih
Input High Voltage
0.5Vcc
Vcc + 0.5
V
Vil
Input Low Voltage
-0.5
0.3Vcc
V
Vipu
Input Pull-up
Voltage
0.7Vcc
V
1
Iil
Input Leakage
Current
0 < Vin < Vcc
+10
μ
A
2
Voh
Output High Voltage Iout = -500
μ
A
0.9Vcc
V
Vol
Output Low Voltage Iout = 1500
μ
A
0.1Vcc
V
Cin
Input Pin
Capacitance
10
pF
3
Cclk
CLK Pin
5
12
pF
相關PDF資料 |
PDF描述 |
|---|---|
| GL9701-MXG | PCI ExpressTM to PCI Bridge |
| GL9711 | PCI ExpressTM PIPE x1 PHY |
| GL9711-TGGXX | PCI ExpressTM PIPE x1 PHY |
| GL9714 | PCI ExpressTM PIPE x4 PHY |
| GL9714-TGGXX | PCI ExpressTM PIPE x4 PHY |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GL9701-MXG | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM to PCI Bridge |
| GL9711 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x1 PHY |
| GL9711-TGGXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x1 PHY |
| GL9714 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x4 PHY |
| GL9714-TGGXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x4 PHY |
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