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參數(shù)資料
| 型號(hào)： | GL9701 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | PCI ExpressTM to PCI Bridge |
| 中文描述： | 的PCI ExpressTM到PCI橋 |
| 文件頁數(shù)： | 47/75頁 |
| 文件大小： | 1077K |
| 代理商： | GL9701 |
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GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 47
or ERR_FATAL transaction (provided the SERR# Enable
bit is set in the Command register). The severity is
selectable only if Advanced Error Reporting is supported.
6
RW
0b
Secondary Bus Reset
–
Forces the assertion of RST
#
on the
secondary interface.
0
–
Do not force the assertion of the secondary interface
RST#.
1
–
Force the assertion of the secondary interface RST#.
7
RO
0b
Fast Back-to-Back Enable
–
Controls ability of the bridge to
generate fast back-to-back transactions to different devices on the
secondary interface.
0
–
Disable generation of fast back-to-back transactions on
the secondary interface.
1
–
Enable generation of fast back-to-back transactions on the
secondary interface.
8
RO
0b
Primary Discard Timer
–
Does not apply to PCI Express.
9
RW
0b
Secondary Discard Timer
–
When in conventional PCI mode,
elects the number of PCI clocks that the bridge will wait for a
master on the secondary interface to repeat a Delayed Transaction
request
0
–
The Secondary Discard Timer counts 215 PCI clock
cycles.
1
–
The Secondary Discard Timer counts 210 PCI clock
cycles.
10
RW
0b
Discard Timer Status
–
This bit is set to a 1 when the Secondary
Discard Timer expires and a Delayed Completion is discarded
from a queue in the bridge.
0
–
No discard timer error.
1
–
Discard timer error.
11
RW
0b
Discard Timer SERR# Enable
–
This bit enables the bridge to
generate either an ERR_NONFATAL (by default) or
ERR_FATAL transaction on the primary interface when the
Secondary Discard Timer expires and a Delayed Transaction is
discarded from a queue in the bridge.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GL9701-MXG | PCI ExpressTM to PCI Bridge |
| GL9711 | PCI ExpressTM PIPE x1 PHY |
| GL9711-TGGXX | PCI ExpressTM PIPE x1 PHY |
| GL9714 | PCI ExpressTM PIPE x4 PHY |
| GL9714-TGGXX | PCI ExpressTM PIPE x4 PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GL9701-MXG | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM to PCI Bridge |
| GL9711 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x1 PHY |
| GL9711-TGGXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x1 PHY |
| GL9714 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x4 PHY |
| GL9714-TGGXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x4 PHY |
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