
GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 50
1
RW
0b
Non-Fatal Error Reporting Enable
–
This bit controls reporting
of Non-fatal errors.
2
RW
0b
Fatal Error Reporting Enable
–
This bit controls reporting of
Fatal errors.
3
RW
0b
Unsupported Request Reporting Enable
–
This bit enables
reporting of Unsupported Requests when set.
4
RW
0b
Enable Relaxed Ordering
–
If this bit is set, the device is
permitted to set the Relaxed Ordering bit in the Attributes field of
transactions it initiates that do not require strong write ordering.
7:5
RW
000b
Max_Payload_Size
–
This field sets maximum TLP payload
size for the device. Permissible values that can be programmed are
indicated by the Max_Payload_Size
Supported in the Device Capabilities register.
8
RO
0b
Extended Tag Field Enable
–
Not supported.
9
RO
0b
Phantom Functions Enable
–
Not supported.
10
RO
0b
Auxiliary (AUX) Power PM Enable
–
Not su[pported.
11
RO
0b
Enable No Snoop
–
GL9701 never sets the No Snoop attribute in
transactions it initiates.
14:12
RW
010b
Max
_
Read_Request
_
Size
–
This field sets the maximum Read
Request size for the Device as a Requester. The Device must not
generate read requests with size exceeding the set value.
15
RsvdP
0b
RsvdP
6.31 Offset 7ah: PCI Express Device Status Register
Bits
Type
Default
Description
0
RW1C
0b
Correctable Error Detected
–
This bit indicates status of
correctable errors detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the
Device Control register.
1
RW1C
0b
Non-Fatal Error Detected
–
This bit indicates status of Nonfatal
errors detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the