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參數(shù)資料
| 型號： | GL9701 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | PCI ExpressTM to PCI Bridge |
| 中文描述： | 的PCI ExpressTM到PCI橋 |
| 文件頁數(shù)： | 24/75頁 |
| 文件大?。?/td> | 1077K |
| 代理商： | GL9701 |
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GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 24
CHAPTER 5 Function Description
5.1 Power Management
GL9701 supports PCI-PM 1.1 Compatible Power Management and Active State Power Management (ASPM)
defined in PCI Express Base Specification Revision 1.0a.
5.1.1 PCI-PM Software Compatible Power Management
GL9701 supports link states L0, L1 and L2 needed to implement PCI-PM compatible power states D0, D1, D2
and D3hot. All link states are determined by the D-state of the bridge. Because GL9711 provides Vaux, bridge
will enter into L2 state when software direct bridge into D3hot state. Refer to the
PCI Express Base
Specification Revision 1.0a
for more protocol information involved in transitioning the link to the L1 or L2
state.
5.1.2 Hardware-Controlled Active State Power Management
GL9701 supports a hardware-initiated power management mechanism which is called Active State Power
Management (ASPM). Once this feature is enabled, bridge will drive the link state into a low-power L0s link
state or even lower-power L1 link state. Refer to the PCI Express Base Specification Revision 1.0a for more
information about ASPM.
Once system software enables GL9701
’
s ASPM capability by setting the ASPM Control bit of Link Control
Register to high, GL9701 will behavior ASPM specified in PCI Express Base Specification Revision 1.0a by
default. However, GL9701 can disable this mechanism via the optional setting specified in table6.1. The
optional bit is the 30
th
bit of Configuration Space Register with offset
‘
hc8. If this bit is set to low, then
GL9701 will never act ASPM behavior no matter what value of the ASPM Control bit of Link Control
Register.
5.1.3 In-band Beacon
Beacon is a in-band signal used to exit the L2 link power management state and informs the Root Complex to
re-activate the link. When the bridge is directed into D3hot State, the link state will finally stay in L2 State.
The device on the secondary PCI bus wakes up the system by asserting PME_N. GL9701 then outputs the
beacon signal on the upstream PCI Express link. Root complex should re-apply the power and reference
clock again after detecting the beacon.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GL9701-MXG | PCI ExpressTM to PCI Bridge |
| GL9711 | PCI ExpressTM PIPE x1 PHY |
| GL9711-TGGXX | PCI ExpressTM PIPE x1 PHY |
| GL9714 | PCI ExpressTM PIPE x4 PHY |
| GL9714-TGGXX | PCI ExpressTM PIPE x4 PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GL9701-MXG | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM to PCI Bridge |
| GL9711 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x1 PHY |
| GL9711-TGGXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x1 PHY |
| GL9714 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x4 PHY |
| GL9714-TGGXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x4 PHY |
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