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參數(shù)資料
| 型號： | GL9701 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | PCI ExpressTM to PCI Bridge |
| 中文描述： | 的PCI ExpressTM到PCI橋 |
| 文件頁數(shù)： | 45/75頁 |
| 文件大?。?/td> | 1077K |
| 代理商： | GL9701 |
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GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 45
0
–
Disable the forwarding of SERR# from the secondary
interface to ERR_FATAL and ERR_NONFATAL
1
–
Enable the forwarding of secondary SERR# to
ERR_FATAL or ERR_NONFATAL.
2
RW
0b
ISA Enable
–
Modifies the response by the bridge to ISA I/O
addresses. This applies only to I/O addresses that are enabled by
the I/O Base and I/O Limit registers and are in the first 64 KB of
PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is
set, the bridge will block any forwarding from primary to
secondary of I/O transactions addressing the last 768 bytes in each
1-KB block. In the opposite direction (secondary to primary), I/O
transactions will be forwarded if they address the last 768 bytes in
each 1-KB block.
0
–
Forward downstream all I/O addresses in the address
range defined by the I/O Base and I/O Limit registers.
1
–
Forward upstream ISA I/O addresses in the address
range defined by the I/O Base and I/O Limit registers that
are in the first 64 KB of PCI I/O address space (top 768
bytes of each 1-KB block).
3
RW
0b
VGA Enable (Optional)
–
Modifies the response of the bridge to
VGA-compatible addresses. If this bit is set, the bridge will
forward the following accesses on the primary interface to the
secondary interface (and, conversely, block the forwarding of these
addresses from the secondary to primary interface):
Memory accesses in the range 000A 0000h to 000B FFFFh
I/O addresses in the first 64 KB of the I/O address space
(Address[31:16] for PCI Express are 0000h) and where
Address[9:0] is in the range of 3B0h to 3BBh or 3C0h to
3DFh (inclusive of ISA address aliases
–
Address[15:10]
may possess any value and is not used in the decoding)
0
–
Do not forward VGA compatible memory and I/O
addresses from the primary to the secondary interface
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GL9701-MXG | PCI ExpressTM to PCI Bridge |
| GL9711 | PCI ExpressTM PIPE x1 PHY |
| GL9711-TGGXX | PCI ExpressTM PIPE x1 PHY |
| GL9714 | PCI ExpressTM PIPE x4 PHY |
| GL9714-TGGXX | PCI ExpressTM PIPE x4 PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GL9701-MXG | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM to PCI Bridge |
| GL9711 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x1 PHY |
| GL9711-TGGXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x1 PHY |
| GL9714 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x4 PHY |
| GL9714-TGGXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x4 PHY |
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