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參數(shù)資料
| 型號： | GL9701 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | PCI ExpressTM to PCI Bridge |
| 中文描述： | 的PCI ExpressTM到PCI橋 |
| 文件頁數(shù)： | 44/75頁 |
| 文件大?。?/td> | 1077K |
| 代理商： | GL9701 |
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GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 44
6.24 Offset 3ch: Interrupt Line Register
Bits
Type
Default
Description
7:0
RW
00h
Interrupt Line: U
sed to communicate interrupt line routing
information. Software will write the routing information into this
register as it initializes and configures the system.
6.25 Offset 3dh: Interrupt Pin Register
Bits
Type
Default
Description
7:0
RO
00h
Interrupt Pin:
GL9701 does not use an interrupt pin.
6.26 Offset 3eh: Bridge Control Register
Bits
Type
Default
Description
0
RW
0b
Parity Error Response Enable
–
Controls the bridge
’
s
response to uncorrectable address, attribute, and data errors on the
secondary interface.
0
–
Ignore uncorrectable address, attribute, and data
errors on the secondary interface.
1
–
Enable uncorrectable address, attribute, and data error
detection and reporting on the secondary interface.
1
RW
0b
SERR# Enable
–
Controls the forwarding of secondary interface
SERR# assertions to the primary interface. The bridge will
transmit an ERR_FATAL or ERR_NONFATAL cycle on the
primary interface when all of the following are true:
SERR# is asserted on the secondary interface
.
This bit is set or Advanced Error Reporting is supported and the
SERR# Assertion Detected Mask bit is clear in the
Secondary Uncorrectable Error Mask register.
The SERR# Enable bit is set in the Command register or the PCI
Express-specific bits are set (refer to Chapter 10 for
details) in the Device Control register of the PCI Express
Capability Structure.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GL9701-MXG | PCI ExpressTM to PCI Bridge |
| GL9711 | PCI ExpressTM PIPE x1 PHY |
| GL9711-TGGXX | PCI ExpressTM PIPE x1 PHY |
| GL9714 | PCI ExpressTM PIPE x4 PHY |
| GL9714-TGGXX | PCI ExpressTM PIPE x4 PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GL9701-MXG | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM to PCI Bridge |
| GL9711 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x1 PHY |
| GL9711-TGGXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x1 PHY |
| GL9714 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x4 PHY |
| GL9714-TGGXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:PCI ExpressTM PIPE x4 PHY |
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