
GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 51
Device Control register.
2
RW1C
0b
Fatal Error Detected
–
This bit indicates status of Fatal errors
detected. Errors are logged in this register regardless of whether
error reporting is enabled or not in the Device Control register.
3
RW1C
0b
Unsupported Request Detected
–
This bit indicates that the
device received an Unsupported Request. Errors are logged in this
register regardless of whether error reporting is enabled or not in
the Device Control register.
4
RO
0b
AUX Power Detected
–
Devices that require AUX power report
this bit as set if AUX power is detected by the device.
5
RO
0b
Transactions Pending
–
This bit when set indicates that the
device has issued Non-Posted Requests which have not been
completed. A device reports this bit cleared only when all
outstanding Non-Posted Requests have completed or have been
terminated by the Completion Timeout mechanism.
15:6
RsvdZ
000h
RsvdZ
6.32 Offset 7ch: PCI Express Link Capabilities Register
Bits
Type
Default
Description
3:0
RO
0001b
Maximum Link Speed
–
This field indicates the maximum Link
speed of the given PCI Express Link. Defined encodings are:
0001b 2.5 Gb/s Link
9:4
RO
00001b
Maximum Link Width
–
This field indicates the maximum width
of the given PCI Express Link.
11:10
RO
00b
Active State Power Management (ASPM) Support
–
Not supported
14:12
RO
111b
L0s Exit Latency
–
This field indicates the L0s exit latency for the
given PCI Express Link.
17:15
RO
111b
L1 Exit Latency
–
This field indicates the L1 exit latency for the
given PCI Express Link.
23:18
RsvdP
00h
RsvdP
31:24
RO
01h
Port Number
–
This field indicates the PCI Express Port