
GL9701 PCI Express
TM
to PCI Bridge
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 36
8
RW1C
0b
Master Data Parity Error
–
This bit is used to report the
detection of uncorrectable data errors by the bridge. This bit is set
if the Parity Error Response bit in the Command register is set and
either of the following two conditions occur:
The bridge receives a Completion with data marked
poisoned on the primary interface.
The bridge poisons a write Request on the primary interface.
0
–
No uncorrectable data error detected on the primary
interface.
1
–
Uncorrectable data error detected on the primary
interface.
10:9
RO
00b
DEVSEL# Timing
–
Does not apply to PCI Express bridges.
Must be hardwired to 00b.
11
RW1C
0b
Signaled Target-Abort
–
This bit is set when the bridge
generates a completion with Completer Abort Completion Status in
response to a request received on its primary interface.
0
–
Completer Abort Completion not transmitted on the
primary interface.
1
–
Completer Abort Completion transmitted on the primary
interface.
12
RW1C
0b
Received Target-Abort
–
This bit is set when the bridge
receives a Completion with Completer Abort Completion Status on
its primary interface.
0
–
Completer Abort Completion Status not received on
primary interface.
1
–
Completer Abort Completion Status received on primary
interface.
13
RW1C
0b
Received Master-Abort
–
This bit is set when the bridge
receives a Completion with Unsupported Request Completion
Status on its primary interface.
0
–
Unsupported Request Completion Status not received on
primary interface.
1
–
Unsupported Request Completion Status received on
primary interface.