
DS3161/DS3162/DS3163/DS3164
10.10.5 C-bit DS3 Framer/Formatter
10.10.5.1 Transmit C-bit DS3 Frame Processor
DS3 Frame.
Table 10-32. C-Bit DS3 Frame Overhead Bit Definitions
Bit
Definition
X1, X2
Remote Defect Indication
(RDI)
P1, P2
Parity Bits
M1, M2, and M3
Multiframe Alignment Bits
FXY
Subframe Alignment Bits
C11
Application Identification
Channel (AIC)
C12
Reserved
C13
Far-End Alarm and Control
(FEAC) signal
C21, C22, and C23
Unused
C31, C32, and C33
C-bit parity bits
C41, C42, and C43
Far-End Block Error (FEBE)
bits
C51, C52, and C53
Path Maintenance Data Link
(or HDLC) bits
C61, C62, and C63
Unused
C71, C72, and C73
Unused
X1 and X2 are the Remote Defect Indication (RDI) bits (also referred to as the far-end SEF/AIS bits). P1 and P2 are
the parity bits used for line error monitoring. M1, M2, and M3 are the multiframe alignment bits. FXY are the subframe
alignment bits. C11 is the Application Identification Channel (AIC). C12 is reserved for future network use, and has a
value of one. C13 is the Far-End Alarm and Control (FEAC) signal. C21, C22, and C23 are unused, and have a value
of one. C31, C32, and C33 are the C-bit parity bits used for path error monitoring. C41, C42, and C43 are the Far-End
Block Error (FEBE) bits used for remote path error monitoring. C51, C52, and C53 are the path maintenance data link
(or HDLC) bits. C61, C62, and C63 are unused, and have a value of one. C71, C72, and C73 are unused, and have a
value of one. The X-bit, P-bit, M-bit, C-bit, and F-bit positions are overhead bits, and the other bit positions in the
DS3 frame are payload bits.
10.10.5.2 Transmit C-bit DS3 Frame Generation
C-bit DS3 frame generation receives the incoming payload data stream, and overwrites the entire overhead bit
locations.
The multiframe alignment bits (M1, M2, and M3) are overwritten with the values zero, one, and zero (010)
respectively.
The subframe alignment bits (FX1, FX2, FX3, and FX4) are overwritten with the values one, zero, zero, and one (1001)
respectively.
The X-bits (X1 and X2) are both overwritten with the Remote Defect Indicator (RDI). The RDI source is
programmable (automatic, 1, or 0). If the T3.TCR.ARDID is one then the T3.TCR.TRDI register bit controls this bit.
If the RDI is generated automatically (T3.TCR.ARDID=0), the X-bits are set to zero when one or more of the