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| 型號(hào)： | DS3160 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 77/107頁 |
| 文件大小： | 592K |
| 代理商： | DS3160 |
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DS3160
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7.3 HDLC Status and Interrupt Register Description
Note:
See Figure 7.2A for details on the signal flow for the status bits in the HSR register.
Register Name:
Register Description:
Register Address:
HSR
HDLC Status Register
38h
Bit #
Name
Default
7
6
5
4
3
2
1
0
TUDR
0
RPE
0
RPS
0
RHWM
0
N/A
0
TLWM
1
N/A
0
TEND
0
Bit #
Name
Default
15
14
13
12
11
10
9
8
RABT
0
REMPTY
1
ROVR
0
TEMPTY
1
TFL3
0
TFL2
0
TFL1
0
TFL0
0
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Transmit Packet End (TEND).
This latched read-only event-status bit is set to a 1 each time the
transmit HDLC controller reads a transmit FIFO byte with the corresponding TMEND bit set, or if an
FIFO underrun occurs. This bit is cleared when read and is not set again until another message end is
detected. The setting of this bit can cause a hardware interrupt to occur if the TEND bit in the interrupt
mask for the HSR (IHSR) register is set to a 1 and the HDLC bit in the interrupt mask for the MSR
(IMSR) register is set to a 1. The interrupt is allowed to clear when this bit is read.
Bit 2/Transmit FIFO Low Watermark (TLWM).
This read-only real-time status bit is set to a 1 when
the transmit FIFO contains less than the number of bytes configured by the transmit low-watermark
setting control bits (TLWMS0 to TLWMS2) in the HDLC control register (HCR). This bit is cleared
when the FIFO fills beyond the low watermark. The setting of this bit can cause a hardware interrupt to
occur if the TLWM bit in the interrupt mask for the HSR (IHSR) register is set to a 1 and the HDLC bit in
the interrupt mask for the MSR (IMSR) register is set to a 1.
Bit 4/Receive FIFO High Watermark (RHWM).
This read-only real-time status bit is set to a 1 when
the receive FIFO contains more than the number of bytes configured by the receive high-watermark
setting control bits (RHWMS0 to RHWMS2) in the HDLC control register (HCR). This bit is cleared
when the FIFO empties below the high watermark. The setting of this bit can cause a hardware interrupt
to occur if the RHWM bit in the interrupt mask for the HSR (IHSR) register is set to a 1 and the HDLC
bit in the interrupt mask for the MSR (IMSR) register is set to a 1.
Bit 5/Receive Packet Start (RPS).
This latched read-only event-status bit is set to a 1 each time the
HDLC controller detects an opening byte of an HDLC packet. This bit is cleared when read and is not set
again until another message is detected. The setting of this bit can cause a hardware interrupt to occur if
the RPS bit in the interrupt mask for the HSR (IHSR) register is set to a 1 and the HDLC bit in the
interrupt mask for the MSR (IMSR) register is set to a 1. The interrupt is allowed to clear when this bit is
read.
Bit 6/Receive Packet End (RPE).
This latched read-only event-status bit is set to a 1 each time the
HDLC controller detects the finish of a message whether the packet is valid (CRC correct) or not (bad
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