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參數(shù)資料
| 型號： | DS3160 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 68/107頁 |
| 文件大小： | 592K |
| 代理商： | DS3160 |
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DS3160
68 of 107
Register Name
Register Description:
Register Address:
BERTEC0
BERT 24-Bit Error Counter (lower) and Status Information
2Eh
Bit #
Name
Default
7
6
5
4
3
2
1
0
N/A
0
RA1
0
RA0
0
RLOS
1
BED
0
BBCO
0
BECO
0
SYNC
0
Bit #
Name
Default
15
14
13
12
11
10
9
8
BEC7
0
BEC6
0
BEC5
0
BEC4
0
BEC3
0
BEC2
0
BEC1
0
BEC0
0
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Real-Time Synchronization Status (SYNC).
Read-only real-time status of the synchronizer (this
bit is not latched). It is set when the incoming pattern matches for 32 consecutive bit positions. It is
cleared when six or more bits out of 64 are received in error. This bit cannot cause a hardware interrupt to
occur.
Bit 1/BERT Error-Counter Overflow (BECO).
A latched read-only event-status bit that is set when the
24-bit BERT error counter (BEC) saturates. Cleared when read and is not set again until another overflow
occurs (i.e., the BEC counter must be cleared and allowed to overflow again). The setting of this status bit
can cause a hardware interrupt to occur if the IEOF bit in BERT control register 0 is set to a 1 and the
BERT bit in the interrupt mask for the MSR (IMSR) register is set to a 1. The interrupt is allowed to clear
when this bit is read (Figure 6.2A).
Bit 2/BERT Bit Counter Overflow (BBCO).
A latched read-only event-status bit that is set when the
32-bit BERT bit counter (BBC) saturates. Cleared when read and is not set again until another overflow
occurs (i.e., the BBC counter must be cleared and allowed to overflow again). The setting of this status bit
can cause a hardware interrupt to occur if the IEOF bit in BERT control register 0 is set to a 1 and the
BERT bit in the interrupt mask for MSR (IMSR) register is set to a 1. The interrupt is allowed to clear
when this bit is read (Figure 6.2A).
Bit 3/Bit Error Detected (BED).
A latched read-only event-status bit that is set when a bit error is
detected. The receive BERT must be in synchronization for it to detect bit errors. This bit is cleared when
read. The setting of this status bit can cause a hardware interrupt to occur if the IEBED bit in BERT
control register 0 is set to a 1 and the BERT bit in the interrupt mask for the MSR (IMSR) register is set
to a 1. The interrupt is allowed to clear when this bit is read (Figure 6.2A).
Bit 4/Receive Loss of Synchronization (RLOS).
A latched read-only alarm-status bit that is set
whenever the receive BERT begins searching for a pattern. Once synchronization is achieved, this bit
remains set until read. A change in this status bit (i.e., the synchronizer goes into or out of
synchronization) can cause a hardware interrupt to occur if the IESYNC bit in BERT control register 0 is
set to a 1 and the BERT bit in the interrupt mask for the MSR (IMSR) register is set to a 1. The interrupt
is allowed to clear when this bit is read (Figure 6.2A).
Bit 5/Receive All 0’s (RA0).
A latched read-only status bit that is set when 31 consecutive 0’s are
received. Allowed to be cleared once a 1 is received. This bit cannot cause a hardware interrupt to occur.
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