參數(shù)資料
型號(hào): DS3160
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 31/107頁
文件大小: 592K
代理商: DS3160
DS3160
31 of 107
Bit 4/Transmit Alarm Indication Signal (TAIS).
When this bit is set high, the transmitter generates an
unframed all 1’s. When this bit it set low, normal data is transmitted.
0 = do not transmit AIS
1 = transmit AIS
Bit 5/Data Enable Mode Select (DENMS).
When this bit is set low, the FRDEN and FTDEN outputs
are asserted during enabled timeslots and deasserted during the disabled timeslots and F-bits of the frame.
When this bit is high, FRDEN and FTDEN are gapped clocks that pulse only during the enabled timeslots
of the frame.
0 = FRDEN and FTDEN are data enables
1 = FRDEN and FTDEN are gapped clocks
Bit 6/Diagnostic Loopback Enable (DLB).
See Figures 1A and 1B for a visual description of this
loopback.
0 = disable loopback
1 = enable loopback
Bit 7/Line Loopback Enable (LLB).
See Figures 1A and 1B for a visual description of this loopback.
0 = disable loopback
1 = enable loopback
Bit 8/Transmit Driver Output Enable (TDRVEN).
When this bit is set low, the Tx+ and Tx- analog
outputs are tri-stated. When this bit is high, the Tx+ and Tx- analog outputs are enabled.
0 = Tx+ and Tx- outputs tri-stated
1 = Tx+ and Tx- outputs enabled
Bit 9/Transmit Monitor Output Enable (TMONEN).
When this bit is set low, the TxMON+ and
TxMON- analog outputs are tri-stated. When this bit is high, the TxMON+ and TxMON- analog outputs
are enabled.
0 = TxMON+ and TxMON- outputs tri-stated
1 = TxMON+ and TxMON- outputs enabled
Bit 10/Receive Monitor Output Enable (RMONEN).
When this bit is set low, the RxMON+ and
RxMON- analog outputs are tri-stated. When this bit is high, the RxMON+ and RxMON- analog outputs
are enabled.
0 = RxMON+ and RxMON- outputs tri-stated
1 = RxMON+ and RxMON- outputs enabled
Bit 11/Jitter Attenuator Enable (JAEN).
When this bit is set low, the jitter attenuator is disabled. When
this bit is high, the jitter attenuator is enabled.
0 = jitter attenuator disabled
1 = jitter attenuator enabled
Bit 12/Jitter Attenuator Path Select (JASEL).
When this bit is set low, the jitter attenuator is enabled in
the receive path. When this bit is high, the jitter attenuator is enabled in the transmit path.
0 = jitter attenuator in receive path
1 = jitter attenuator in transmit path
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