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參數(shù)資料
| 型號： | DS3160 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 37/107頁 |
| 文件大小： | 592K |
| 代理商： | DS3160 |
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DS3160
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Master Status Register (MSR)
The master status register (MSR) is a special status register that can be used to help the host quickly
locate changes in device status. There is a status bit in the MSR for each of the major blocks within the
DS3160. When an alarm or event occurs in one of these blocks, the device can be configured to set a bit
in the MSR. Status bits in the MSR can also cause a hardware interrupt to occur. In either polled or
interrupt-driven software routines, the host can first read the MSR to locate which status registers need to
be serviced.
Register Name:
Register Description:
Register Address:
MSR
Master Status Register
06h
Bit #
Name
Default
7
6
5
4
3
2
1
0
N/A
0
N/A
0
N/A
0
SR1
0
HDLC
0
BERT
0
COVF
0
OST
0
Bit #
Name
Default
15
N/A
0
14
N/A
0
13
N/A
0
12
N/A
0
11
10
9
8
TXDRVR
0
LIULOS
1
N/A
0
LOTC
1
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/One-Second-Timer Boundary Occurrence (OST).
This latched read-only event status bit is set to
a 1 on each 1-second boundary as timed by the DS3160. The device chooses an arbitrary 1-second
boundary that is timed from the RCLK signal. This bit is cleared when read and is not be set again until
another 1-second boundary has occurred. The setting of this status bit can cause a hardware interrupt to
occur if the OST bit in the interrupt mask for MSR (IMSR) register is set to a 1. The interrupt is allowed
to clear when this bit is read.
Bit 1/Counter Overflow Event (COVF).
This latched read-only event status bit is set to a 1 if any of the
error counters saturate (the error counters saturate when full). This bit is cleared when read even if one or
more of the error counters is still saturated. The setting of this status bit can cause a hardware interrupt to
occur if the COVF bit in the interrupt mask for MSR (IMSR) register is set to a 1. The interrupt is allowed
to clear when this bit is read.
Bit 2/Change in BERT Status (BERT).
This read-only event status bit is set to a 1 if there is a major
change of status in the BERT receiver. A major change of status is defined as either a change in the
receive synchronization (i.e., the BERT has gone into or out of receive synchronization), a bit error has
been detected, or an overflow has occurred in either the bit counter or the error counter. The host must
read the status bits of the BERT in the BERT status register (BERTEC0) to determine the change of state.
This bit is cleared when read and is not set again until the BERT has experienced another change of state.
The setting of this status bit can cause a hardware interrupt to occur if the BERT bit in the interrupt mask
for MSR (IMSR) register is set to a 1 (Figure 4.3D).
Bit 3/Change in HDLC Status (HDLC).
This read-only event status bit is set to a 1 if there is a change
of status in the HDLC controller. The host must read the status bits of the HDLC controller in the HDLC
status register (HSR) to determine the change of state. This bit is cleared when read and is not set again
until the HDLC controller has experienced another change of state. The setting of this status bit can cause
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