參數(shù)資料
型號(hào)： DS3160
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 38/107頁(yè)
文件大小： 592K
代理商： DS3160
DS3160
38 of 107
a hardware interrupt to occur if the HDLC bit in the interrupt mask (IMSR) register is set to a 1 (Figure
4.3E).
Bit 4/Change in Framer Status (SR1).
This read-only event-status bit is set to a 1 if there is a change of
status in the framer or formatter. The host must read the contents of SR1 to determine the change of state.
This bit is cleared when read and is not set again until the framer or formatter has experienced another
change of state. The setting of this status bit can cause a hardware interrupt to occur if the SR1 bit in the
interrupt mask (IMSR) register is set to a 1 (Figure 4.3F).
Bit 8/Loss-of-Transmit Clock Detected (LOTC).
This latched read-only alarm status bit is set to a 1
when the device detects that the FTCLK clock has not toggled for 200ns (±100ns). This bit is cleared
when a clock is detected at the FTCLK input. The setting of this status bit can cause a hardware interrupt
to occur if the LOTC bit in the interrupt mask for MSR (IMSR) register is set to a 1. The interrupt is
allowed to clear when the device detects a clock at FTCLK. On reset, the LOTC status bit is set and then
immediately cleared if the clock is present.
Bit 10/Analog Loss-of-Signal Detected (LIULOS).
This latched read-only alarm status bit is set to a 1
when the device detects that the incoming signal has dropped below -20dB of the nominal signal level.
When set, the recovered data is squelched and all 0’s are output to the framer. The analog loss-of-signal
detector is not clear until the signal level is above -16dB of the nominal signal level. Setting this status bit
can cause a hardware interrupt to occur if the LIULOS bit in the interrupt mask for MSR (IMSR) register
is set to a 1.
Bit 11/Transmit Driver Monitor (TXDRVR).
This latched read-only alarm status bit is set to a 1 when
the analog-transmit outputs (Tx+ and Tx-) fail. The setting of this status bit can cause a hardware
interrupt to occur if the TXDRVR bit in the interrupt mask for MSR (IMSR) register is set to a 1.
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