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參數(shù)資料
| 型號(hào)： | DS3160 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 54/107頁 |
| 文件大?。?/td> | 592K |
| 代理商： | DS3160 |
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DS3160
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interrupt mask for MSR (IMSR) register is set to a 1. The interrupt is allowed to clear when this bit is
read. The RAI alarm detection criteria is described in Table 5.3A.
Bit 5/Transmit Start of Frame (TSOF).
This latched read-only event-status bit is set to a 1 on each
transmit frame or multiframe boundary (see FTSOFM). This bit is a software version of the FTSOF
hardware signal and it is cleared when read. The setting of this bit can cause a hardware interrupt to occur
if the TSOF bit in the interrupt mask for SR1 (ISR1) register is set to a 1 and the SR1 bit in the interrupt
mask for MSR (IMSR) register is set to a 1.
Bit 6/Receive Start of Frame (RSOF).
This latched read-only event-status bit is set to a 1 on each
receive frame or multiframe boundary (see FRSOFM). This bit is a software version of the FRSOF
hardware signal and it is cleared when read. The setting of this bit can cause a hardware interrupt to occur
if the RSOF bit in the interrupt mask for SR1 (ISR1) register is set to a 1 and the SR1 bit in the interrupt
mask for MSR (IMSR) register is set to a 1.
Bit 7/Receive Change-of-Frame Alignment (RCOFA).
This latched read-only event-status bit is set to a
1 when the framer has experienced a change-of-frame alignment (COFA). A COFA occurs when the
device achieves synchronization in a different alignment than it had previously. If the device has never
acquired synchronization before, then this status bit is meaningless. This bit is cleared when read and is
not set again until the framer has lost synchronization and reacquired synchronization in a different
alignment. The setting of this bit can cause a hardware interrupt to occur if the RCOFA bit in the interrupt
mask for SR1 (ISR1) register is set to a 1 and the SR1 bit in the interrupt mask for MSR (IMSR) register
is set to a 1.
Bit 8/Remote-End Alarm Detected (READ).
This latched read-only alarm-status bit is set to a 1 when
the framer detects a remote-end alarm (A-bit set to 1). This bit is cleared when read unless the remote-end
alarm signal is present. A change in state of the remote-end alarm can cause a hardware interrupt to occur
if the READ bit in the interrupt mask for SR1 (ISR1) register is set to a 1 and the SR1 bit in the interrupt
mask for the MSR (IMSR) register is set to a 1. The interrupt is allowed to clear when this bit is read. The
READ threshold can be set in CR2.
Bit 9/False-Frame Alignment (FFA).
This latched read-only event-status bit is set to a 1 when 32
consecutive super frames have bad CRC. This feature can be used to assist in monitoring for false-frame
alignment as described in JT-G706. This bit is cleared when read. The setting of this bit can cause a
hardware interrupt to occur if the RSOF bit in the interrupt mask for SR1 (ISR1) register is set to a 1 and
the SR1 bit in the interrupt mask for the MSR (IMSR) register is set to a 1.
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