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| 型號(hào)： | DS3160 |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 53/107頁(yè) |
| 文件大?。?/td> | 592K |
| 代理商： | DS3160 |
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DS3160
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5.3 Framer Status and Interrupt Register Descriptions
Note:
See Figure 5.3A for details about the signal flow for the status bits in the SR register.
Register Name:
Register Description:
Register Address:
SR1
Status Register
12h
Bit #
Name
Default
6
5
4
3
2
1
0
RCOFA
0
RSOF
0
TSOF
0
RAI
0
AIS
0
CRCER
0
LOF
1
LOS
1
Bit #
Name
Default
15
N/A
0
14
N/A
0
13
N/A
0
12
N/A
0
11
N/A
0
10
N/A
0
9
8
FFA
0
READ
0
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Loss-of-Signal Occurrence (LOS).
This latched read-only alarm-status bit is set to a 1 when the
framer detects a loss of signal. The signal FRD is forced to all 1’s during an LOS condition. This bit is
cleared when read unless an LOS condition still exists. A change in state of the LOS can cause a hardware
interrupt to occur if the LOS bit in the interrupt mask for the SR1 (ISR1) register is set to a 1 and the SR1
bit in the interrupt mask for the MSR (IMSR) register is set to a 1. The interrupt is allowed to clear when
this bit is read. The LOS alarm criteria is described in Table 5.3A.
Bit 1/Loss-of-Frame Occurrence (LOF).
This latched read-only alarm-status bit is set to a 1 when the
framer detects a loss of frame. This bit is cleared when read unless an LOF condition still exists. A change
in state of the LOF can cause a hardware interrupt to occur if the LOF bit in the interrupt mask for the
SR1 (ISR1) register is set to a 1 and the SR1 bit in the interrupt mask for the MSR (IMSR) register is set
to a 1. The interrupt is allowed to clear when this bit is read. The LOF alarm criteria is described in Table
5.3A.
Bit 2/Receive CRC Error Detected (CRCER).
This latched read-only event-status bit is set to a 1 as a
result of detecting a CRC error in a received multiframe. This bit is cleared when read. The setting of this
bit can cause a hardware interrupt to occur if the CRCER bit in the interrupt mask for the SR1 (ISR1)
register is set to a 1 and the SR1 bit in the interrupt mask for the MSR (IMSR) register is set to a 1.
Bit 3/Alarm Indication Signal Detected (AIS).
This latched read-only alarm-status bit is set to a 1 when
the framer detects an incoming alarm indication signal. This bit is cleared when read unless an AIS signal
is still present. A change in state of the AIS detection can cause a hardware interrupt to occur if the AIS
bit in the interrupt mask for SR1 (ISR1) register is set to a 1 and the SR1 bit in the interrupt mask for
MSR (IMSR) register is set to a 1. The interrupt is allowed to clear when this bit is read. The AIS alarm
detection criteria is described in Table 5.3A.
Bit 4/Remote Alarm Indication Detected (RAI).
This latched read-only alarm-status bit is set to a 1
when the framer detects an incoming remote alarm indication (RAI) signal. This bit is cleared when read
unless an RAI signal is still present. A change in state of the RAI detection can cause a hardware interrupt
to occur if the RAI bit in the interrupt mask for SR1 (ISR1) register is set to a 1 and the SR1 bit in the
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