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參數資料
| 型號： | DS3160 |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數： | 73/107頁 |
| 文件大?。?/td> | 592K |
| 代理商： | DS3160 |
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DS3160
73 of 107
7.2 HDLC Control and FIFO Register Description
Register Name:
Register Description:
Register Address:
HCR
HDLC Control Register
32h
Bit #
Name
Default
7
6
5
4
3
2
1
0
N/A
0
RHR
0
THR
0
TFS
0
N/A
0
TCRCI
0
TZSD
0
TCRCD
0
Bit #
Name
Default
15
14
13
12
11
10
9
8
RHWMS2
0
RHWMS1
0
RHWMS0
0
TLWMS2
0
TLWMS1
0
TLWMS0
0
RID
0
TID
0
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Transmit CRC Defeat (TCRCD).
When this bit is set low, the HDLC automatically calculates and
appends the 16-bit CRC to the outgoing HDLC message. When this bit is set high, the device does not
append the CRC to the outgoing message.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
Bit 1/Transmit Zero Stuffer Defeat (TZSD).
When this bit is set low, the HDLC automatically enables
the zero stuffer in between the opening and closing flags of the HDLC message. When this bit is set high,
the device does not enable the zero stuffer under any condition.
0 = enable zero stuffer (normal operation)
1 = disable zero stuffer
Bit 2/Transmit CRC Invert (TCRCI).
When this bit is set low, the HDLC allows the CRC to be
generated normally. When this bit is set high, the device inverts all 16 bits of the generated CRC. This bit
is ignored when the CRC generation is disabled (TCRCD = 1). This bit is useful in testing HDLC
operation.
0 = do not invert the generated CRC (normal operation)
1 = invert the generated CRC
Bit 4/Transmit Flag/Idle Select (TFS).
This control bit determines whether flags or idle bytes are
transmitted in between packets.
0 = 7Eh (flags)
1 = FFh (idle)
Bit 5/Transmit HDLC Reset (THR).
A 0-to-1 transition resets the transmit HDLC controller. Must be
cleared and set again for a subsequent reset. A reset flushes the current contents of the transmit FIFO and
causes one FEh abort sequence (seven 1’s in a row) to be sent followed by either 7Eh (flags) or FFh (idle)
until a new packet is initiated by writing new data (at least two bytes) into the FIFO.
Bit 6/Receive HDLC Reset (RHR).
A 0-to-1 transition resets the receive HDLC controller. Must be
cleared and set again for a subsequent reset. A reset flushes the current contents of the receive FIFO and
causes the receive HDLC controller to begin searching for a new incoming HDLC packet.
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