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參數(shù)資料
| 型號(hào)： | DS21FT42 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 99/145頁 |
| 文件大?。?/td> | 466K |
| 代理商： | DS21FT42 |
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DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1239
Data may be parallel-loaded into the Test Data registers selected by the current instruction. If the instruction
does not call for a parallel load or the selected register does not allow parallel loads, the Test register will remain
at its current value. On the rising edge of JTCLK, the controller will go to the Shift-DR state if JTMS is low or it
will go to the Exit1-DR state if JTMS is high.
Shift-DR
The Test Data register selected by the current instruction will be connected between JTDI and JTDO and will
shift data one stage towards its serial output on each rising edge of JTCLK. If a Test Register selected by the
current instruction is not placed in the serial path, it will maintain its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR state, and
terminate the scanning process. A rising edge on JTCLK with JTMS low will put the controller in the Pause-DR
state.
Pause-DR
Shifting of the test registers is halted while in this state. All Test registers selected by the current instruction will
retain their previous state. The controller will remain in this state while JTMS is low. A rising edge on JTCLK
with JTMS high will put the controller in the Exit2-DR state.
Exit2-DR
While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR state and
terminate the scanning process. A rising edge on JTCLK with JTMS low will enter the Shift-DR state.
Update-DR
A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the Test
registers into the data output latches. This prevents changes at the parallel output due to changes in the shift
register. A rising edge on JTCLK with JTMS low, will put the controller in the Run-Test-Idle state. With JTMS
high, the controller will enter the Select-DR-Scan state.
Select-IR-Scan
All test registers retain their previous state. The instruction register will remain unchanged during this state. With
JTMS low, a rising edge of JTCLK moves the controller into the Capture-IR state and will initiate a scan
sequence for the Instruction register. JTMS high during a rising edge on JTCLK puts the controller back into the
Test-Logic-Reset state.
Capture-IR
The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is
loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller will enter the
Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller will enter the Shift-IR state.
Shift-IR
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| DS21FT42N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4X3 E1 Framer E1 Framer E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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