參數(shù)資料
型號(hào): DS21FT42
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 93/145頁
文件大小: 466K
代理商: DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1233
21. TRANSMIT TRANSPARENCY
Each of the 24 T1 channels in the transmit direction of the framer can be either
forced to be transparent or in other words, can be forced to stop Bit 7 Stuffing
and/or Robbed Signaling from overwriting the data in the channels.
Transparency can be invoked on a channel by channel basis by properly setting
the TTR1, TTR2, and TTR3 registers.
TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTER
(Address=39 to 3B Hex)
(MSB)
CH8
CH16
CH24
(LSB)
CH1
CH9
CH17
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
TTR1 (39)
TTR2 (3A)
TTR3 (3B)
SYMBOLS
POSITIONS
NAME AND DESCRIPTION
CH1-24
TTR1.0-3.7
Transmit Transparency Registers.
0 = this DS0 channel is not transparent
1 = this DS0 channel is transparent
Each of the bit position in the Transmit Transparency Registers (TTR1/TTR2/TTR3)
represent a DS0 channel in the outgoing frame. When these bits are set to a one, the
corresponding channel is transparent (or clear). If a DS0 is programmed to be clear, no
robbed bit signaling will be inserted nor will the channel have Bit 7 stuffing performed.
However, in the D4 framing mode, bit 2 will be overwritten by a zero when a Yellow Alarm
is transmitted. Also the user has the option to prevent the TTR registers from determining
which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set
to one, then all 24 T1 channels will have Bit 7 stuffing performed on them regardless of how
the TTR registers are programmed. In this manner, the TTR registers are only affecting
which channels are to have robbed bit signaling inserted into them. Please see Figure 24-15
for more details.
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