參數(shù)資料
型號(hào): DS21FT42
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 105/145頁
文件大?。?/td> 466K
代理商: DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/105
This register contains both a shift register path and a latched parallel output for all control
cells and digital I/O cells and is 126 bits in length. Table 23-4 shows all of the cell bit
locations and definitions.
Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and
HIGHZ instructions, which provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output.
This register is selected during the IDCODE instruction and when the TAP controller is in
the Test-Logic-Reset state.
Boundary Scan Register Description
Table 23-4
MCM
LEAD
(DIE1)
B7
G20
H20
G19
H19
G18
H18
G17
H17
W15
-
MCM
LEAD
(DIE2)
MCM
LEAD
(DIE3)
MCM
LEAD
(DIE4)
SCAN
REGISTER
BIT
102
60
59
58
57
56
55
54
37
22
94
DS21Q42
DIE
SYMBOL
8MCLK
A0
A1
A2
A3
A4
A5
A6/ALE (AS)
A7
BTS
BUS.cntl
TYPE
CONTROL BIT
DESCRIPTION
O
I
I
I
I
I
I
I
I
I
-
G20
H20
G19
H19
G18
H18
G17
H17
W15
G20
H20
G19
H19
G18
H18
G17
H17
W15
G20
H20
G19
H19
G18
H18
G17
H17
W15
0 = D0-D7 or AD0-
AD7 are inputs
1 = D0-D7 or AD0-
AD7 are outputs
B6
T8
L20
M20
L19
M19
L18
M18
L17
M17
Y14
W14
100
23
93
92
91
90
89
88
87
86
25
24
CLKSI
CS*
D0 or AD0
D1 or AD1
D2 or AD2
D3 or AD3
D4 or AD4
D5 or AD5
D6 or AD6
D7 or AD7
FS0
FS1
I
I
Y4
L20
M20
L19
M19
L18
M18
L17
M17
Y14
W14
Y15
L20
M20
L19
M19
L18
M18
L17
M17
Y14
W14
E19
L20
M20
L19
M19
L18
M18
L17
M17
Y14
W14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
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