參數(shù)資料
型號: DS21FT42
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 97/145頁
文件大?。?/td> 466K
代理商: DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1237
23. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
23.1
Description
The DS21Q42 IEEE 1149.1 design supports the standard instruction codes
SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included
with this design are HIGHZ, CLAMP, and IDCODE. See Figure 23-1 for a block diagram.
The DS21Q42 contains the following items, which meet the requirements, set by the IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture.
The DS21FT42 should
be considered as 3 individual DS21Q42 devices. The DS21FF42 should be considered as 4
individual DS21Q42 devices.
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The JTAG feature is only available when the DS21Q42 feature set is selected (FMS = 0).
The JTAG feature is disabled when the DS21Q42 is configured for emulation of the
DS21Q41B (FMS = 1).
FMS is tied to ground for the DS21FF42/DS21FT42.
Details on
Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990,
IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins; JTRST*, JTCLK, JTMS, JTDI, and
JTDO. See the pin descriptions for details.
Boundary Scan Architecture
Figure 23-1
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