參數(shù)資料
型號: DS21FT42
元件分類: 通信及網(wǎng)絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 71/145頁
文件大?。?/td> 466K
代理商: DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1231
16. CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit
Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and
TCHBLK pins respectively. The RCHBLK and TCHCLK pins are user programmable
outputs that can be forced either high or low during individual channels. These outputs can
be used to block clocks to a USART or LAPD controller in Fractional T1 or ISDN–PRI
applications. When the appropriate bits are set to a one, the RCHBLK and TCHCLK pins
will be held high during the entire corresponding channel time. See the timing in Section
24 for an example.
RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS
(Address=6C to 6E Hex)
(MSB)
CH8
CH16
CH24
(LSB)
CH1
CH9
CH17
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
RCBR1 (6C)
RCBR2 (6D)
RCBR3 (6E)
SYMBOLS
CH1 - 24
POSITIONS
RCBR1.0 - 3.7
NAME AND DESCRIPTION
Receive Channel Blocking Control Bits.
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address=32 to 34 Hex)
(MSB)
CH8
CH16
CH24
(LSB)
CH1
CH9
CH17
CH7
CH15
CH23
CH6
CH14
CH22
CH5
CH13
CH21
CH4
CH12
CH20
CH3
CH11
CH19
CH2
CH10
CH18
TCBR1 (32)
TCBR2 (33)
TCBR3 (34)
SYMBOLS
CH1 - 24
POSITIONS
TCBR1.0 - 3.7
NAME AND DESCRIPTION
Transmit Channel Blocking Control Bits.
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
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