參數(shù)資料
型號(hào)： DS21FT42
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 23/145頁
文件大小： 466K
代理商： DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1233
Signal Description:
Signal Type:
A user programmable output that can be forced high or low during any of the 24 T1
channels. Synchronous with RCLK when the receive side elastic store is disabled.
Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for
blocking clocks to a serial UART or LAPD controller in applications where not all T1
channels are used such as Fractional T1, 384K bps service, 768K bps, or ISDN–PRI. Also
useful for locating individual channels in drop–and–insert applications, for external per–
channel loopback, and for per–channel conditioning. See Section 16 for details.
Receive Channel Block
Output
Signal Name:
Signal Description:
Signal Type:
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic
store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic
store is enabled.
RSER
Receive Serial Data
Output
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame
(RCR2.4 = 0) or multiframe (RCR2.4 = 1) boundaries. If set to output frame boundaries
then via RCR2.5, RSYNC can also be set to output double–wide pulses on signaling
frames. If the receive side elastic store is enabled via CCR1.2, then this pin can be enabled
to be an input via RCR2.3 at which a frame or multiframe boundary pulse is applied. See
Section 24 for details.
RSYNC
Receive Sync
Input /Output
Signal Name:
Signal Description:
Signal Type:
An extracted 8 KHz pulse, one RCLK wide, is output at this pin which identifies frame
boundaries.
This signal is not bonded out in the DS21FF42/DS21FT42.
RFSYNC
Receive Frame Sync
Output
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe
boundaries. If the receive side elastic store is disabled, then this output will output
multiframe boundaries associated with RCLK. This function is available when FMS = 1
(DS21Q41 emulation).
This signal is not bonded out in the DS21FF42/DS21FT42.
RMSYNC
Receive Multiframe Sync
Output
Signal Name:
RSYSCLK
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21FT42N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4X3 E1 Framer E1 Framer E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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