參數(shù)資料
型號: DS21FT42
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 35/145頁
文件大?。?/td> 466K
代理商: DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1235
SYNCC
RCR1.3
Sync Criteria.
In D4 Framing Mode.
0 = search for Ft pattern, then search for Fs pattern
1 = cross couple Ft and Fs pattern
In ESF Framing Mode.
0 = search for FPS pattern only
1 = search for FPS and verify with CRC6
Sync Time.
0 = qualify 10 bits
1 = qualify 24 bits
Sync Enable.
0 = auto resync enabled
1 = auto resync disabled
Resync.
When toggled from low to high, a resynchronization of the
receive side framer is initiated. Must be cleared and set again for a
subsequent resync.
SYNCT
RCR1.2
SYNCE
RCR1.1
RESYNC
RCR1.0
RCR2: RECEIVE CONTROL REGISTER 2
(Address=2C Hex)
(MSB)
RCS
(LSB)
MOSCRF
RZBTSI
RSDW
RSM
RSIO
RD4YM
FSBE
SYMBOL
POSITION
NAME AND DESCRIPTION
RCS
RCR2.7
Receive Code Select.
See Section 15 for more details.
0 = idle code (7F Hex)
1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex)
Receive Side ZBTSI Enable.
0 = ZBTSI disabled
1 = ZBTSI enabled
RSYNC Double–Wide.
(note: this bit must be set to zero when RCR2.4
= 1 or when RCR2.3 = 1)
0 = do not pulse double wide in signaling frames
1 = do pulse double wide in signaling frames
RSYNC Mode Select.
(A Don’t Care if RSYNC is programmed as an
input)
0 = frame mode (see the timing in Section 24)
1 = multiframe mode (see the timing in Section 24)
RSYNC I/O Select.
(note: this bit must be set to zero when CCR1.2 =
0)
0 = RSYNC is an output
1 = RSYNC is an input (only valid if elastic store enabled)
Receive Side D4 Yellow Alarm Select.
0 = zeros in bit 2 of all channels
1 = a one in the S–bit position of frame 12
RZBTSI
RCR2.6
RSDW
RCR2.5
RSM
RCR2.4
RSIO
RCR2.3
RD4YM
RCR2.2
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