參數(shù)資料
型號： DS21FT42
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 66/145頁
文件大小： 466K
代理商： DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1236
15. PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK
Each framer in the DS21Q42 can replace data on a channel–by–channel basis in both the
transmit and receive directions. The transmit direction is from the backplane to the T1 line
and is covered in Section 15.1. The receive direction is from the T1 line to the backplane
and is covered in Section 15.2.
15.1
TRANSMIT SIDE CODE GENERATION
In the transmit direction there are two methods by which channel data from the backplane
can be overwritten with data generated by the framer. The first method which is covered in
Section 15.1.1 was a feature contained in the original DS21Q41 while the second method
which is covered in Section 15.1.2 is a new feature of the DS21Q42.
15.1.1
Simple Idle Code Insertion and Per–Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3) to determine which
of the 24 T1 channels should be overwritten with the code placed in the Transmit Idle
Definition Register (TIDR). This method allows the same 8–bit code to be placed into any
of the 24 T1 channels. If this method is used, then the CCR4.0 control bit must be set to
zero.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3) represent a DS0
channel in the outgoing frame. When these bits are set to a one, the corresponding channel
will transmit the Idle Code contained in the Transmit Idle Definition Register (TIDR).
Robbed bit signaling and Bit 7 stuffing will occur over the programmed Idle Code unless
the DS0 channel is made transparent by the Transmit Transparency Registers.
The Transmit Idle Registers (TIRs) have an alternate function that allow them to define a
Per–Channel LoopBack (PCLB). If the TIRFS control bit (CCR4.0) is set to one, then the
TIRs will determine which channels (if any) from the backplane should be replaced with the
data from the receive side or in other words, off of the T1 line. If this mode is enabled, then
transmit and receive clocks and frame syncs must be synchronized. One method to
accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS
(Address=3C to 3E Hex)
[Also used for Per–Channel Loopback]
(MSB)
CH8
(LSB)
CH1
CH7
CH6
CH5
CH4
CH3
CH2
TIR1 (3C)
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DS21FT42N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4X3 E1 Framer E1 Framer E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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DS21FT44N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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