參數(shù)資料
型號： DS21FT42
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 73/145頁
文件大?。?/td> 466K
代理商： DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1233
fills, then a full frame of data will be deleted and the SR1.4 and RIR1.4 bits will be set to a
one.
17.2
TRANSMIT SIDE
The operation of the transmit elastic store is very similar to the receive side. The transmit
side elastic store is enabled via CCR1.7. A 1.544 MHz (CCR1.4=0) or 2.048 MHz
(CCR1.4=1) clock can be applied to the TSYSCLK input. If the user selects to apply a
2.048 MHz clock to the TSYSCLK pin, then the data input at TSER will be ignored every
fourth channel. Hence channels 1 (except for the MSB), 5, 9, 13, 17, 21, 25, and 29
(timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be ignored. A special case exists for the
MSB of channel 1. Via TCR1.6 the MSB of channel 1 can be sampled as the F-bit. The
user must supply a 8 KHz frame sync pulse to the TSSYNC input. Also, in 2.048 MHz
applications, the TCHBLK output will be forced high during the channels ignored by the
framer. See Section 23 for more details. Controlled slips in the transmit elastic store are
reported in the RIR2.3 bit and the direction of the slip is reported in the RIR2.5 and RIR2.4
bits.
17.3
MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE
In applications where the framer is connected to backplanes that are frequency locked to the
recovered T1 clock (i.e., the RCLK output), the full two frame depth of the onboard elastic
stores is really not needed. In fact, in some delay sensitive applications, the normal two
frame depth may be excessive. Register bits CCR3.7 and CCR3.0 control the RX and TX
elastic stores depths. In this mode, RSYSCLK and TSYSCLK must be tied together and
they must be frequency locked to RCLK. All of the slip contention logic in the framer is
disabled (since slips cannot occur). Also, since the buffer depth is no longer two frames
deep, the framer must be set up to source a frame pulse at the RSYNC pin and this output
must be tied to the TSSYNC input. On power–up after the RSYSCLK and TSYSCLK
signals have locked to the RCLK signal, the elastic stores should be reset.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21FT42N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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DS21FT44N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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