參數(shù)資料
型號： DS21FT42
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 76/145頁
文件大?。?/td> 466K
代理商： DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1236
messages as described in AT&T TR54016. The HDLC controller automatically generates
and detects flags, generates and checks the CRC check sum, generates and detects abort
sequences, stuffs and destuffs zeros (for transparency), and byte aligns to the HDLC data
stream. The 64–byte buffers in the HDLC controller are large enough to allow a full PRM to
be received or transmitted without host intervention. The BOC controller will automatically
detect incoming BOC sequences and alert the host. When the BOC ceases, the DS21Q42
will also alert the host. The user can set the device up to send any of the possible 6–bit
BOC codes.
There are thirteen registers that the host will use to operate and control the operation of the
HDLC and BOC controllers. A brief description of the registers is shown in Table 19–1.
HDLC/BOC CONTROLLER REGISTER LIST
Table 19-1
NAME
FUNCTION
HDLC Control Register (HCR)
general control over the HDLC and BOC
controllers
HDLC Status Register (HSR)
key status information for both transmit and
receive directions
HDLC Interrupt Mask Register (HIMR)
allows/stops status bits to/from causing an interrupt
Receive HDLC Information Register (RHIR)
status information on receive HDLC controller
Receive BOC Register (RBOC)
status information on receive BOC controller
Receive HDLC FIFO Register (RHFR)
access to 64–byte HDLC FIFO in receive direction
Receive HDLC DS0 Control Register 1 (RDC1)
Receive HDLC DS0 Control Register 2 (RDC2)
controls the HDLC function when used on DS0
channels
Transmit HDLC Information Register (THIR)
status information on transmit HDLC controller
Transmit BOC Register (TBOC)
enables/disables transmission of BOC codes
Transmit HDLC FIFO Register (THFR)
access to 64–byte HDLC FIFO in transmit direction
Transmit HDLC DS0 Control Register 1 (TDC1)
Transmit HDLC DS0 Control Register 2 (TDC2)
controls the HDLC function when used on DS0
channels
19.1.2
Status Register for the HDLC
Four of the HDLC/BOC controller registers (HSR, RHIR, RBOC, and THIR) provide
status information. When a particular event has occurred (or is occurring), the appropriate bit
in one of these four registers will be set to a one. Some of the bits in these four HDLC status
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DS21FT44N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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