參數(shù)資料
型號: DS21FT42
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 67/145頁
文件大小: 466K
代理商: DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1237
CH16
CH24
CH15
CH23
CH14
CH22
CH13
CH21
CH12
CH20
CH11
CH19
CH10
CH18
CH9
CH17
TIR2 (3D)
TIR3 (3E)
SYMBOLS
POSITIONS
NAME AND DESCRIPTION
CH1 - 24
TIR1.0 - 3.7
Transmit Idle Code Insertion Control Bits.
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
NOTE:
If CCR4.0=1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one implies that
channel data is to be sourced from the output of the receive side framer (i.e., Per–Channel Loopback; see Figure
6–1).
TIDR: TRANSMIT IDLE DEFINITION REGISTER
(Address=3F Hex)
(MSB)
TIDR7
(LSB)
TIDR0
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
SYMBOL
POSITION
NAME AND DESCRIPTION
TIDR7
TIDR0
TIDR.7
TIDR.0
MSB of the Idle Code (this bit is transmitted first)
LSB of the Idle Code (this bit is transmitted last)
15.1.2
Per–Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3) to
determine which of the 24 T1 channels should be overwritten with the code placed in the
Transmit Channel Registers (TC1 to TC24). This method is more flexible than the first in
that it allows a different 8–bit code to be placed into each of the 24 T1 channels.
TC1 TO TC24: TRANSMIT CHANNEL REGISTERS
(Address=40 to 4F and 50 to 57 Hex)
(for brevity, only channel one is shown; see Table 8-1 for other register address)
(MSB)
C7
(LSB)
C0
C6
C5
C4
C3
C2
C1
TC1 (50)
SYMBOL
POSITION
NAME AND DESCRIPTION
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